git.libre-soc.org Git - soc.git/history - src/soc/fu/trap/trap_input

[soc.git] / src / soc / fu / trap / trap_input_record.py

2022-01-25	Luke Kenneth Casso...	LDSTException now passing bits of SRR1 around to the...	commit \| commitdiff
2021-07-14	Luke Kenneth Casso...	update SVSTATE to 64 bit length (fortunately very easy)	commit \| commitdiff
2021-05-04	Luke Kenneth Casso...	add SVSTATE (SVSRR0) to TRAP pipeline	commit \| commitdiff
2021-04-26	Luke Kenneth Casso...	hook up MSR into MMU (TODO, use a lot less bits)	commit \| commitdiff
2021-04-23	Luke Kenneth Casso...	more openpower-isa conversion	commit \| commitdiff
2021-04-23	Luke Kenneth Casso...	move over to from openpower imports	commit \| commitdiff
2020-10-06	Luke Kenneth Casso...	passing LDSTException over to Trap Pipeline	commit \| commitdiff
2020-10-06	Luke Kenneth Casso...	add LDSTException decode/handling in PowerDecoder2	commit \| commitdiff
2020-07-22	Luke Kenneth Casso...	add TT.size and use it in PowerDecoder and trap input...	commit \| commitdiff
2020-07-21	Luke Kenneth Casso...	move cia and msr to trap input record	commit \| commitdiff
2020-07-15	Luke Kenneth Casso...	use new CompOpSubsetBase in trap	commit \| commitdiff
2020-07-12	Luke Kenneth Casso...	rename InternalOp to MicrOp	commit \| commitdiff
2020-07-08	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	commit \| commitdiff
2020-07-05	Luke Kenneth Casso...	big reorg on PowerDecoder2, actually Decode2Execute1Type	commit \| commitdiff
2020-07-04	Luke Kenneth Casso...	cater for illegal instruction (generates a trap)	commit \| commitdiff
2020-07-01	Luke Kenneth Casso...	start running trap unit test, fixing errors	commit \| commitdiff

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