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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
trap
/ trap_input_record.py
2022-01-25
Luke Kenneth Casso...
LDSTException now passing bits of SRR1 around to the...
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2021-07-14
Luke Kenneth Casso...
update SVSTATE to 64 bit length (fortunately very easy)
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2021-05-04
Luke Kenneth Casso...
add SVSTATE (SVSRR0) to TRAP pipeline
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2021-04-26
Luke Kenneth Casso...
hook up MSR into MMU (TODO, use a lot less bits)
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2021-04-23
Luke Kenneth Casso...
more openpower-isa conversion
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2020-10-06
Luke Kenneth Casso...
passing LDSTException over to Trap Pipeline
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2020-10-06
Luke Kenneth Casso...
add LDSTException decode/handling in PowerDecoder2
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2020-07-22
Luke Kenneth Casso...
add TT.size and use it in PowerDecoder and trap input...
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2020-07-21
Luke Kenneth Casso...
move cia and msr to trap input record
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2020-07-15
Luke Kenneth Casso...
use new CompOpSubsetBase in trap
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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2020-07-04
Luke Kenneth Casso...
cater for illegal instruction (generates a trap)
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2020-07-01
Luke Kenneth Casso...
start running trap unit test, fixing errors
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