move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / trap /
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline
2021-05-04 Luke Kenneth Casso... adding fast3 SPR to Trap pipeline and unit test
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-23 Luke Kenneth Casso... add trap test cases
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-10-16 Luke Kenneth Casso... experiment swapping dummy trap stage over to input
2020-10-16 Luke Kenneth Casso... add extra (test dummy stage in trap to see if combinato...
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-06 Luke Kenneth Casso... comment, nothing unusual when Trap Type is DEC
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-14 Luke Kenneth Casso... hrfid unit test sets up HSRR0 and HSRR1
2020-08-14 Luke Kenneth Casso... hack to get hrfid not to alter msr 51
2020-08-14 Luke Kenneth Casso... add hrfid unit test
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth Casso... whoops fix change of variable (state) msr/pc
2020-08-04 Samuel A. Falvo IIRemove XXX; this seems done otherwise.
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayformat some tests
2020-07-28 Luke Kenneth Casso... tidyup/comments in trap proof
2020-07-27 Luke Kenneth Casso... fix trap proof, and trap main_stage, and pseudocode...
2020-07-27 Luke Kenneth Casso... shorten expected_ to exp_, gets line-length down
2020-07-26 Samuel A. Falvo IIMTMSR(D) properties.
2020-07-26 Luke Kenneth Casso... convert TRAP test to accumulator style
2020-07-25 Luke Kenneth Casso... update comment-headers (TODO include page numbers to...
2020-07-25 Luke Kenneth Casso... make trap proof section more readable
2020-07-24 Samuel A. Falvo IIProperties for MFMSR
2020-07-24 Samuel A. Falvo IIReorganize code layout
2020-07-24 Samuel A. Falvo IIWIP: SC properties more closely match doc'd behavior
2020-07-24 Samuel A. Falvo IIWIP: addressing code review, restoring proofs, etc.
2020-07-24 Luke Kenneth Casso... got fed up with bit-slice ordering crap. cut it out
2020-07-24 Luke Kenneth Casso... code review comments for trap and proof
2020-07-24 Samuel A. Falvo IIRefactorin of common code
2020-07-24 Samuel A. Falvo IIAddress code review comments
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-22 Luke Kenneth Casso... whoops forgot field accessor
2020-07-22 Luke Kenneth Casso... whoops typo, 63-start not 3-start (doh)
2020-07-22 Luke Kenneth Casso... field number ordering wrong way round?
2020-07-22 Luke Kenneth Casso... syntax error
2020-07-22 Luke Kenneth Casso... review trap main_stage.py modifications: we are not...
2020-07-22 Luke Kenneth Casso... add comment headings with spec page numbers
2020-07-22 Luke Kenneth Casso... comment on op.insn ordering
2020-07-22 Luke Kenneth Casso... code-shuffle, add comments
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-22 Luke Kenneth Casso... inline comments in trap proof
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions.
2020-07-22 Samuel A. Falvo IIPEP8 compliance
2020-07-21 Samuel A. Falvo IICompleted SC FV properties
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties.
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware
2020-07-21 Luke Kenneth Casso... corrections to trap proof see
2020-07-21 Luke Kenneth Casso... use alias for msr_i in trap proof
2020-07-21 Luke Kenneth Casso... correct trap spec page interrupt ref
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style
2020-07-20 Samuel A. Falvo IIFormal properties for RFID.
2020-07-18 Luke Kenneth Casso... whoops use slice not range
2020-07-18 Luke Kenneth Casso... syntax error
2020-07-18 Luke Kenneth Casso... add comment and copy of pseudo-code for OP_RFID into...
2020-07-18 Luke Kenneth Casso... review of OP_RFID showed up some errors
2020-07-18 Luke Kenneth Casso... corrections to trap main_stage.py OP_RFID according...
2020-07-18 Samuel A. Falvo IIWIP: FV failing for unknown reasons.
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-18 Samuel A. Falvo IIFailing test: fast1/fast2 vs srr0/srr1? on trap pipe
2020-07-18 Samuel A. Falvo IIforgot to clean up workspace in source
2020-07-18 Samuel A. Falvo IIFV props for SC instruction
2020-07-17 Samuel A. Falvo IIFirst FV property for trap unit
2020-07-16 Luke Kenneth Casso... add mfmsr trap tests
2020-07-15 Luke Kenneth Casso... use new CompOpSubsetBase in trap
2020-07-15 Luke Kenneth Casso... remove unneeded comment in trap msin stage
2020-07-15 Luke Kenneth Casso... remove unneeded comment in trap pipe_data
2020-07-15 Luke Kenneth Casso... move traptype to soc.consts
2020-07-15 Luke Kenneth Casso... test privileged rfid call
2020-07-15 Luke Kenneth Casso... set MSR up properly for privileged mtmsr test
2020-07-14 Luke Kenneth Casso... adding MSR.PR unit test intended to activate privileged...
2020-07-13 Luke Kenneth Casso... add mtmsrd instruction and unit test
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-06 Luke Kenneth Casso... adding OP_MTMSR test
2020-07-05 Luke Kenneth Casso... add mtmsr tests (fail)
2020-07-05 Luke Kenneth Casso... check msr in trap test, fix OP_RFID
2020-07-05 Luke Kenneth Casso... add an illegal instruction trap test
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... check NIA on trap fu test
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