move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu /
32 hours ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
32 hours ago Jacob Lifshayfix mul fu test helper.py not passing immediate to...
34 hours ago Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
4 days ago Cesar StraussFix rel_o/go_i signal names
4 days ago Cesar StraussFix import
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-31 Luke Kenneth Casso... anooother valid_o to convert to o_valid
2021-08-31 Luke Kenneth Casso... update ready/valid in shift_rot test_pipe_caller
2021-08-31 Jacob Lifshayfix test_all_values_covered, missed import when moving...
2021-08-30 Luke Kenneth Casso... update ready/valid i/o_ prefix in div test helper.py
2021-08-30 Luke Kenneth Casso... fix ready/valid i/o prefix in ALU test
2021-08-30 Luke Kenneth Casso... fix CR tests valid/ready naming
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-07-23 Tobias Platenldst: cleanup debug outputs
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-11 Tobias Platenpass self.pi.is_dcbz to request
2021-06-18 Tobias Platensrc/soc/fu/ldst/loadstore.py: keep data for the whole...
2021-06-10 Luke Kenneth Casso... whoops Popcount datalen too big (wasted bits). reduce
2021-05-14 Luke Kenneth Casso... clear out request data on return to idle
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-12 Luke Kenneth Casso... set m_out.load from ldst_r(egister) in LoadStore1
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... add MSR to LD/ST Input Record
2021-05-11 Luke Kenneth Casso... comment tidyup
2021-05-11 Luke Kenneth Casso... must also pass through instruction fault exception...
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM
2021-05-11 Luke Kenneth Casso... tidyup comments and remove LoadStore COMPLETE state
2021-05-11 Luke Kenneth Casso... cleanup on exception setting
2021-05-11 Luke Kenneth Casso... rename LoadStore1 data structures back to microwatt...
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1
2021-05-10 Luke Kenneth Casso... move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP
2021-05-09 Luke Kenneth Casso... add comments on translation of MMU_LOOKUP
2021-05-09 Luke Kenneth Casso... install MMU_LOOKUP vhdl to be translated to nmigen
2021-05-09 Luke Kenneth Casso... move (unused) ACK_WAIT code into FSM
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1
2021-05-09 Luke Kenneth Casso... remove invalid setting of d_in.valid from self.mmureq
2021-05-09 Luke Kenneth Casso... no SECOND_REQ
2021-05-09 Luke Kenneth Casso... remove SECOND_REQ
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid
2021-05-09 Tobias Platenmove skeleton to elaborate
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add in alignment exception capture/reporting in LoadStore1
2021-05-09 Luke Kenneth Casso... preference is to create a temp variable for comb and...
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-08 Luke Kenneth Casso... LoadStore1 tidyup
2021-05-08 Luke Kenneth Casso... transferring more over to LoadStore FSM
2021-05-08 Luke Kenneth Casso... start putting state info into LoadStore1, slowly puttin...
2021-05-08 Luke Kenneth Casso... add LoadStore State enum
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc...
2021-05-07 Luke Kenneth Casso... start setting DSISR bits but commented out
2021-05-07 Luke Kenneth Casso... update comments and docstrings
2021-05-07 Luke Kenneth Casso... whoops, import error
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore
2021-05-07 Luke Kenneth Casso... whoops was still copying output over in CommonOutputStage
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1
2021-05-07 Luke Kenneth Casso... move zero-dest-pred in Common Output Stage to not copy...
2021-05-06 Luke Kenneth Casso... if zeroing is set, put zero into input or output as...
2021-05-05 Tobias Platenfix bug in mmu/fsm.py
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline
2021-05-04 Tobias Platenupate dsisr and dar using sync
2021-05-04 Luke Kenneth Casso... adding fast3 SPR to Trap pipeline and unit test
2021-05-04 Luke Kenneth Casso... add printout showing exception output from FUs
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o...
2021-05-04 Luke Kenneth Casso... remove exception from data on FUBaseData, explicitly...
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit
2021-05-04 Luke Kenneth Casso... add LDSTException class to LDSTOutputData
2021-05-04 Luke Kenneth Casso... add option to add exception type to FUBaseData (pipe_data)
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-05-04 Luke Kenneth Casso... comment out nc (nocache), it seems to actually work
2021-05-03 Luke Kenneth Casso... MMU: get store to activate only when data is available...
2021-05-03 Luke Kenneth Casso... disable the cache for now, whilst testing read/write...
2021-05-02 Luke Kenneth Casso... use Const to define bit-length when comparing top nibbl...
2021-05-02 Luke Kenneth Casso... mmu FSM store in dcache: only put data onto d_in on...
2021-05-02 Luke Kenneth Casso... return d_out.valid instead of always "ok" in MMU FSM
2021-05-02 Luke Kenneth Casso... HACK WARNING: disable d-cache on hard-coded address...
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth Casso... only do dcache lookup for now
2021-04-30 Luke Kenneth Casso... debug and stop on mmu test_pipe_caller.py
2021-04-30 Luke Kenneth Casso... comments on dcache-to-mmu link
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... hook up dcache wb_in/out to PortInterfaceBase Wishbone...
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