| 2023-09-12 |
Jacob Lifshay | remove grev, leaving tests for later use with grevlut |
tree | commitdiff |
| 2023-09-11 |
Jacob Lifshay | skip madd* tests since they're not implemented |
tree | commitdiff |
| 2023-09-11 |
Jacob Lifshay | MASK was moved into ISACallerHelper class |
tree | commitdiff |
| 2023-09-11 |
Jacob Lifshay | set parent pspec to class with XLEN = 64 |
tree | commitdiff |
| 2023-09-11 |
Jacob Lifshay | set 'soc' filter to filter out v3.1 insns |
tree | commitdiff |
| 2023-09-11 |
Jacob Lifshay | fix ALU test by setting 'soc' filter to filter out... |
tree | commitdiff |
| 2022-08-16 |
Jacob Lifshay | change goldschmidt_div_sqrt to use nmutil.plain_data... |
tree | commitdiff |
| 2022-07-05 |
Luke Kenneth Casso... | MulOutputData was only 64-bit output not 128-bit |
tree | commitdiff |
| 2022-07-04 |
Luke Kenneth Casso... | add signal for resetting trap internal state (kaivb... |
tree | commitdiff |
| 2022-07-04 |
Luke Kenneth Casso... | set msr_o.data not msr_o Record in trap main_stage.py |
tree | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | adapt TRAP function in main state pipeline to put KAIVB |
tree | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | store KAIVB SPR 850 in TRAP Pipeline |
tree | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | update trap test_pipe_caller.py to use up-to-date test... |
tree | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | missing module argument to TestRunner execute |
tree | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | convert trap test_pipe_caller.py to consistent format |
tree | commitdiff |
| 2022-05-01 |
Luke Kenneth Casso... | split out front of div into separate stage, still too... |
tree | commitdiff |
| 2022-04-30 |
Luke Kenneth Casso... | add missing module |
tree | commitdiff |
| 2022-04-30 |
Luke Kenneth Casso... | split off CR0/XER production in DIV Function Unit into... |
tree | commitdiff |
| 2022-04-30 |
Luke Kenneth Casso... | clear out DEC in core.cur_state.dec due to spurious... |
tree | commitdiff |
| 2022-04-29 |
Jacob Lifshay | fix waay-too-precise error requirements |
tree | commitdiff |
| 2022-04-29 |
Jacob Lifshay | add comment |
tree | commitdiff |
| 2022-04-29 |
Jacob Lifshay | fix so HDL works for 5, 8, 16, 32, and 64-bits. |
tree | commitdiff |
| 2022-04-29 |
Jacob Lifshay | HDL works for io_width=5 |
tree | commitdiff |
| 2022-04-28 |
Jacob Lifshay | add docs for clz |
tree | commitdiff |
| 2022-04-28 |
Jacob Lifshay | add WIP HDL version of goldschmidt division -- it's... |
tree | commitdiff |
| 2022-04-28 |
Jacob Lifshay | move GoldschmidtDivState |
tree | commitdiff |
| 2022-04-28 |
Jacob Lifshay | add FIXME comments |
tree | commitdiff |
| 2022-04-28 |
Jacob Lifshay | add the goldschmidt sqrt/rsqrt algorithm, still need... |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | improved goldschmidt division algorithm parameter optim... |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | split out non-derived params into separate class withou... |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | split out n_hat as separate property |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | add default_cost_fn |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | move GoldschmidtDivParams.get to bottom of class |
tree | commitdiff |
| 2022-04-27 |
Jacob Lifshay | rename _goldschmidt_div_ops to GoldschmidtDivState... |
tree | commitdiff |
| 2022-04-26 |
Jacob Lifshay | goldschmidt division works! still needs better paramete... |
tree | commitdiff |
| 2022-04-26 |
Jacob Lifshay | fix goofed __init__.py file name |
tree | commitdiff |
| 2022-04-25 |
Jacob Lifshay | working on goldschmidt_div_sqrt.py |
tree | commitdiff |
| 2022-04-23 |
Jacob Lifshay | working on goldschmidt division algorithm |
tree | commitdiff |
| 2022-04-22 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
| 2022-04-22 |
Jacob Lifshay | add WIP goldschmidt division algorithm |
tree | commitdiff |
| 2022-03-12 |
Luke Kenneth Casso... | add extra pipeline stages to ALU FU to make timing |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | bit_length is 1 more than needed: subtract 1 from XLEN... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix up shift_rot test_pipe_caller to new regspeckls... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | convert shift_rot pipeline to XLEN=32/64 |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix up Logical pipeline to produce HDL with XLEN=32 |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | whoops ALU common output target must be XLEN-bit, |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | set up dummy parent_pspec to pass XLEN=64 in |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | start on converting MUL and DIV pipelines to XLEN |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | convert from public static functions/properties for... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix ALU with XLEN=32, carry and overflow |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | use XLEN in Function Units (starting with ALU) |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add running instructions |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for shift/rot o.ok |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | clean up code |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCR |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCL |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLC |
tree | commitdiff |
| 2022-02-23 |
Luke Kenneth Casso... | forgot to pass cix (cache-inhibited) through to LD... |
tree | commitdiff |
| 2022-02-22 |
Jacob Lifshay | speed up shift/rot formal proof by running stuff in... |
tree | commitdiff |
| 2022-02-21 |
Luke Kenneth Casso... | again reduce combinatorial chains, similar to Trap... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | same as shiftrot, split out separate pipelines for... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | nope, it's perfectly fine |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | weird exception, oe not found in the shiftrot input... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | separate out shiftrot stages due to size of main stage... |
tree | commitdiff |
| 2022-02-18 |
Jacob Lifshay | add grev |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "remove dummy trap pipeline" |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "doh" |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | doh |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | remove dummy trap pipeline |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | in LoadStore1 capture the address for misaligned dual... |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | sort out misaligned store in LoadStore1 |
tree | commitdiff |
| 2022-01-27 |
Luke Kenneth Casso... | for second aligned request truncate address to nearest... |
tree | commitdiff |
| 2022-01-25 |
Luke Kenneth Casso... | LDSTException now passing bits of SRR1 around to the... |
tree | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | bool test on traptype to |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | skip ilang data in branch test_pipe_caller.py |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | attempting to get compunit and test_pipe_caller unit... |
tree | commitdiff |
| 2022-01-20 |
Luke Kenneth Casso... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | ISI (0x400) trap is the only one that puts memory-based... |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | move DEC and TB into StateRegs, to make room in FastRegs |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | comments on SRR1 in trap |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | preserve bits of SRR1 on a TRAP (including all interrup... |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | fix hrfid and mtmsrd so that it is identical to microwatt |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | raise interrupt on misaligned atomic LDST |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | pass over store_done correctly from dcache over PortInt... |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | add CR0 to LDSTCompUnit, for reporting if LR/SC store... |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass over atomic signals to dcache from loadstore. |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass atomic reserve through from PortInterface to DCache |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | add reserve (atomic) signal to LDST data structures... |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | fix issue with priv_mode not being passed correctly... |
tree | commitdiff |
| 2022-01-10 |
Luke Kenneth Casso... | LoadStore1 priv_mode was not being correctly picked... |
tree | commitdiff |
| 2022-01-09 |
Luke Kenneth Casso... | add linux-5.7 unit test which showed a silly error: |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | fix MMU lookup after 2nd request (misaligned) by also... |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | do not clear out ldst request after TLB entry is added |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | add a second LD request to dcache which is merged with... |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | start adding in mis-aligned LD/ST support into LoadStore1 |
tree | commitdiff |
| 2022-01-06 |
Luke Kenneth Casso... | add SECOND_REQ state to loadstore.py, not yet implemented |
tree | commitdiff |
| 2022-01-03 |
Luke Kenneth Casso... | adding an extra option to issuer_verilog.py to be able... |
tree | commitdiff |
| 2021-12-30 |
Luke Kenneth Casso... | rename nia to cia in MMU input record and mmu FSM |
tree | commitdiff |
| 2021-12-28 |
Luke Kenneth Casso... | add misaligned mmu.bin test 5 notes: currently LoadStor... |
tree | commitdiff |
| 2021-12-26 |
Luke Kenneth Casso... | rename addr to raddr in LoadStore1 to avoid conflict... |
tree | commitdiff |
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