split out front of div into separate stage, still too long combinatorial
[soc.git] / src / soc / fu /
2022-05-01 Luke Kenneth Casso... split out front of div into separate stage, still too... master
2022-04-30 Luke Kenneth Casso... add missing module
2022-04-30 Luke Kenneth Casso... split off CR0/XER production in DIV Function Unit into...
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious...
2022-04-29 Jacob Lifshayfix waay-too-precise error requirements
2022-04-29 Jacob Lifshayadd comment
2022-04-29 Jacob Lifshayfix so HDL works for 5, 8, 16, 32, and 64-bits.
2022-04-29 Jacob LifshayHDL works for io_width=5
2022-04-28 Jacob Lifshayadd docs for clz
2022-04-28 Jacob Lifshayadd WIP HDL version of goldschmidt division -- it's...
2022-04-28 Jacob Lifshaymove GoldschmidtDivState
2022-04-28 Jacob Lifshayadd FIXME comments
2022-04-28 Jacob Lifshayadd the goldschmidt sqrt/rsqrt algorithm, still need...
2022-04-27 Jacob Lifshayimproved goldschmidt division algorithm parameter optim...
2022-04-27 Jacob Lifshaysplit out non-derived params into separate class withou...
2022-04-27 Jacob Lifshaysplit out n_hat as separate property
2022-04-27 Jacob Lifshayadd default_cost_fn
2022-04-27 Jacob Lifshaymove GoldschmidtDivParams.get to bottom of class
2022-04-27 Jacob Lifshayrename _goldschmidt_div_ops to GoldschmidtDivState...
2022-04-26 Jacob Lifshaygoldschmidt division works! still needs better paramete...
2022-04-26 Jacob Lifshayfix goofed __init__.py file name
2022-04-25 Jacob Lifshayworking on goldschmidt_div_sqrt.py
2022-04-23 Jacob Lifshayworking on goldschmidt division algorithm
2022-04-22 Luke Kenneth Casso... whitespace
2022-04-22 Jacob Lifshayadd WIP goldschmidt division algorithm
2022-03-12 Luke Kenneth Casso... add extra pipeline stages to ALU FU to make timing
2022-02-27 Luke Kenneth Casso... bit_length is 1 more than needed: subtract 1 from XLEN...
2022-02-27 Luke Kenneth Casso... fix up shift_rot test_pipe_caller to new regspeckls...
2022-02-27 Luke Kenneth Casso... convert shift_rot pipeline to XLEN=32/64
2022-02-27 Luke Kenneth Casso... fix up Logical pipeline to produce HDL with XLEN=32
2022-02-27 Luke Kenneth Casso... whoops ALU common output target must be XLEN-bit,
2022-02-27 Luke Kenneth Casso... set up dummy parent_pspec to pass XLEN=64 in
2022-02-27 Luke Kenneth Casso... start on converting MUL and DIV pipelines to XLEN
2022-02-27 Luke Kenneth Casso... convert from public static functions/properties for...
2022-02-27 Luke Kenneth Casso... fix ALU with XLEN=32, carry and overflow
2022-02-27 Luke Kenneth Casso... use XLEN in Function Units (starting with ALU)
2022-02-24 Jacob Lifshayadd running instructions
2022-02-24 Jacob Lifshayadd formal proof for shift/rot o.ok
2022-02-24 Jacob Lifshayclean up code
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCR
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCL
2022-02-24 Jacob Lifshayadd formal proof for OP_RLC
2022-02-23 Luke Kenneth Casso... forgot to pass cix (cache-inhibited) through to LD...
2022-02-22 Jacob Lifshayspeed up shift/rot formal proof by running stuff in...
2022-02-21 Luke Kenneth Casso... again reduce combinatorial chains, similar to Trap...
2022-02-20 Luke Kenneth Casso... same as shiftrot, split out separate pipelines for...
2022-02-20 Luke Kenneth Casso... nope, it's perfectly fine
2022-02-20 Luke Kenneth Casso... weird exception, oe not found in the shiftrot input...
2022-02-20 Luke Kenneth Casso... separate out shiftrot stages due to size of main stage...
2022-02-18 Jacob Lifshayadd grev
2022-02-13 Luke Kenneth Casso... Revert "remove dummy trap pipeline"
2022-02-13 Luke Kenneth Casso... Revert "doh"
2022-01-31 Luke Kenneth Casso... doh
2022-01-31 Luke Kenneth Casso... remove dummy trap pipeline
2022-01-28 Luke Kenneth Casso... in LoadStore1 capture the address for misaligned dual...
2022-01-28 Luke Kenneth Casso... sort out misaligned store in LoadStore1
2022-01-27 Luke Kenneth Casso... for second aligned request truncate address to nearest...
2022-01-25 Luke Kenneth Casso... LDSTException now passing bits of SRR1 around to the...
2022-01-24 Luke Kenneth Casso... bool test on traptype to
2022-01-21 Luke Kenneth Casso... skip ilang data in branch test_pipe_caller.py
2022-01-21 Luke Kenneth Casso... attempting to get compunit and test_pipe_caller unit...
2022-01-20 Luke Kenneth Casso... whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
2022-01-19 Luke Kenneth Casso... ISI (0x400) trap is the only one that puts memory-based...
2022-01-19 Luke Kenneth Casso... move DEC and TB into StateRegs, to make room in FastRegs
2022-01-18 Luke Kenneth Casso... comments on SRR1 in trap
2022-01-18 Luke Kenneth Casso... preserve bits of SRR1 on a TRAP (including all interrup...
2022-01-17 Luke Kenneth Casso... fix hrfid and mtmsrd so that it is identical to microwatt
2022-01-16 Luke Kenneth Casso... raise interrupt on misaligned atomic LDST
2022-01-16 Luke Kenneth Casso... pass over store_done correctly from dcache over PortInt...
2022-01-16 Luke Kenneth Casso... add CR0 to LDSTCompUnit, for reporting if LR/SC store...
2022-01-15 Luke Kenneth Casso... pass over atomic signals to dcache from loadstore.
2022-01-15 Luke Kenneth Casso... pass atomic reserve through from PortInterface to DCache
2022-01-15 Luke Kenneth Casso... add reserve (atomic) signal to LDST data structures...
2022-01-12 Luke Kenneth Casso... fix issue with priv_mode not being passed correctly...
2022-01-10 Luke Kenneth Casso... LoadStore1 priv_mode was not being correctly picked...
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error:
2022-01-08 Luke Kenneth Casso... fix MMU lookup after 2nd request (misaligned) by also...
2022-01-08 Luke Kenneth Casso... do not clear out ldst request after TLB entry is added
2022-01-08 Luke Kenneth Casso... add a second LD request to dcache which is merged with...
2022-01-08 Luke Kenneth Casso... start adding in mis-aligned LD/ST support into LoadStore1
2022-01-06 Luke Kenneth Casso... add SECOND_REQ state to loadstore.py, not yet implemented
2022-01-03 Luke Kenneth Casso... adding an extra option to issuer_verilog.py to be able...
2021-12-30 Luke Kenneth Casso... rename nia to cia in MMU input record and mmu FSM
2021-12-28 Luke Kenneth Casso... add misaligned mmu.bin test 5 notes: currently LoadStor...
2021-12-26 Luke Kenneth Casso... rename addr to raddr in LoadStore1 to avoid conflict...
2021-12-22 Luke Kenneth Casso... when setting DSISR in LoadStore1 use correct load bit...
2021-12-22 Luke Kenneth Casso... use correct X-Form L field in OP_MTMSRD
2021-12-22 Luke Kenneth Casso... check problem state in OP_MTMSRD from original reg...
2021-12-22 Luke Kenneth Casso... remove unneeded state in LoadStore1
2021-12-22 Luke Kenneth Casso... clear instruction fault on exception WAIT_MMU ACK in...
2021-12-22 Luke Kenneth Casso... clear out instr_fault when exception is thrown
2021-12-22 Luke Kenneth Casso... clear instruction fault on idle/valid in Loadstore1
2021-12-21 Luke Kenneth Casso... for each unit test case in test_issuer_mmu_data_path...
2021-12-21 Luke Kenneth Casso... test_issuer_mmu_data_path.py needs to use wb_get because of
2021-12-20 Luke Kenneth Casso... unit tests for SPRs when MMU enabled,
2021-12-18 Luke Kenneth Casso... forgot to connect up I-Cache to MMU
2021-12-14 Luke Kenneth Casso... get OP_FETCH_FAILED to respond/return an exception...
2021-12-14 Luke Kenneth Casso... MMU LOOKUP for fetch failed, priv mode is inversion...
2021-12-14 Luke Kenneth Casso... link MSR.PR into MMU FSM OP_FETCH_FAILED
2021-12-13 Luke Kenneth Casso... convert LoadStore1 to new msr.pr/dr/sf
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