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whoops missed some cases in unit test changing ALUHelpers
[soc.git]
/
src
/
soc
/
fu
/
2020-07-01
Luke Kenneth Casso...
whoops missed some cases in unit test changing ALUHelpers
tree
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commitdiff
2020-07-01
Luke Kenneth Casso...
whoops swapped trap test instructions accidentally
tree
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commitdiff
2020-07-01
Luke Kenneth Casso...
attempting to add SPRs to rfid test
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commitdiff
2020-07-01
Luke Kenneth Casso...
trap test check results
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commitdiff
2020-07-01
Luke Kenneth Casso...
add in trap compunit
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commitdiff
2020-07-01
Luke Kenneth Casso...
add rfid and td/tw trap test
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commitdiff
2020-07-01
Luke Kenneth Casso...
continue debugging trap pipeline
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commitdiff
2020-07-01
Luke Kenneth Casso...
debugging trap pipeline
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commitdiff
2020-07-01
Luke Kenneth Casso...
start running trap unit test, fixing errors
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commitdiff
2020-06-30
Luke Kenneth Casso...
code-morph on div pipeline
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commitdiff
2020-06-29
Luke Kenneth Casso...
add README for fu directory
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commitdiff
2020-06-29
Luke Kenneth Casso...
use correct ALUHelpers in div test
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commitdiff
2020-06-29
Luke Kenneth Casso...
sort out syntax errors in div
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commitdiff
2020-06-29
Luke Kenneth Casso...
first unit test for div
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commitdiff
2020-06-28
Luke Kenneth Casso...
got Pi2LSUI FSM working
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commitdiff
2020-06-27
Luke Kenneth Casso...
make Memory accessible via TestSRAMBareLoadStoreUnit
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commitdiff
2020-06-27
Luke Kenneth Casso...
increase (double) address width in TstL0CacheBuffer
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commitdiff
2020-06-22
Luke Kenneth Casso...
simplified L0CacheBuffer down to a "PortInterface Arbiter"
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commitdiff
2020-06-19
Luke Kenneth Casso...
whitespace update
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commitdiff
2020-06-18
Jacob Lifshay
div pipe completed except for tests
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commitdiff
2020-06-18
Jacob Lifshay
finish code to calculate the 64-bit output of the div...
tree
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commitdiff
2020-06-18
Jacob Lifshay
actually remove todo comment for manually checking...
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commitdiff
2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-06-18
Jacob Lifshay
fix bug and manually check div overflow code against...
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commitdiff
2020-06-18
Luke Kenneth Casso...
use while / exception in test_compunit loop
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commitdiff
2020-06-18
Jacob Lifshay
working on adding rest of stage classes for div pipeline
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commitdiff
2020-06-17
Luke Kenneth Casso...
decoding assembly instruction name, move to separate...
tree
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commitdiff
2020-06-17
Luke Kenneth Casso...
get fu compunit test to use ISACaller instruction-memory
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commitdiff
2020-06-17
Luke Kenneth Casso...
start to add in independent execution into ISACaller
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commitdiff
2020-06-17
Luke Kenneth Casso...
use an independent power decoder in ISACaller
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commitdiff
2020-06-16
Luke Kenneth Casso...
update popcount docstring
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commitdiff
2020-06-15
Luke Kenneth Casso...
move setup/check memory into helper functions for use...
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commitdiff
2020-06-15
Luke Kenneth Casso...
whoops LDSTCompUnit was identified as a Function.ALU...
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commitdiff
2020-06-15
Luke Kenneth Casso...
add in TstL0CacheBuffer but disable temporarily
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commitdiff
2020-06-14
Luke Kenneth Casso...
add optional LDSTFunctionUnit to compunits
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commitdiff
2020-06-14
Luke Kenneth Casso...
unit tests showing byte-reverse works
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commitdiff
2020-06-14
Luke Kenneth Casso...
reasonably certain that the careful and slow use of...
tree
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commitdiff
2020-06-12
Luke Kenneth Casso...
update ld/st test to see what is going on
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commitdiff
2020-06-12
Luke Kenneth Casso...
tracking down what looks like an error in the Simulator...
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commitdiff
2020-06-12
Luke Kenneth Casso...
debug printout of sim and hardware memory, shows mismat...
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commitdiff
2020-06-12
Luke Kenneth Casso...
use ALUHelpers in LDSTCompUnit test
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commitdiff
2020-06-11
Luke Kenneth Casso...
some ugly hacks that get LD/ST immediate working
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commitdiff
2020-06-11
Luke Kenneth Casso...
even more complexity in CompALUMulti, to deal with...
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commitdiff
2020-06-11
Luke Kenneth Casso...
must distinguish between rd/write xer_ca sim helpers
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commitdiff
2020-06-11
Luke Kenneth Casso...
fixing get_rd_sim_xer_ca, has to only read carry if...
tree
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commitdiff
2020-06-11
Luke Kenneth Casso...
yield needed for unit tests to work (has to go)
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commitdiff
2020-06-11
Luke Kenneth Casso...
read and write version of get_sim_xer_ca are different
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commitdiff
2020-06-11
Luke Kenneth Casso...
use ALUHelpers in shift_rot
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commitdiff
2020-06-11
Luke Kenneth Casso...
add fast spr1/2 sim ALUHelpers
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commitdiff
2020-06-11
Luke Kenneth Casso...
rename get_sim_cr_a to get_wr_sim_cr_a for now
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commitdiff
2020-06-10
Luke Kenneth Casso...
whitespace
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commitdiff
2020-06-10
Luke Kenneth Casso...
link ST.go directly to ST.rel
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commitdiff
2020-06-10
Luke Kenneth Casso...
add link to bug 361 in FU test
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commitdiff
2020-06-10
Luke Kenneth Casso...
TODO on RA immediate-zero mode
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commitdiff
2020-06-10
Luke Kenneth Casso...
re-do cookie-cut of alu test_pipe_caller.py over to...
tree
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commitdiff
2020-06-10
Luke Kenneth Casso...
use ALUHelpers in output stage of test_pipe_caller
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commitdiff
2020-06-10
Luke Kenneth Casso...
use sim-get helpers in ALU input fetch
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commitdiff
2020-06-10
Luke Kenneth Casso...
use ALUHelpers in output phase of test_alu_compunit.py
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commitdiff
2020-06-10
Luke Kenneth Casso...
continue ALUHelpers check alu outputs code-morph
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commitdiff
2020-06-10
Luke Kenneth Casso...
code-morph ALU output test check phase
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commitdiff
2020-06-10
Luke Kenneth Casso...
starting on alu output check
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commitdiff
2020-06-10
Luke Kenneth Casso...
ilang file output change from alu_pipeline.il to div_pi...
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commitdiff
2020-06-10
Luke Kenneth Casso...
cookie-cut alu test_pipe_caller.py over
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commitdiff
2020-06-10
Luke Kenneth Casso...
move to common ALUHelpers for ShiftRot test_pipe_caller.py
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commitdiff
2020-06-10
Luke Kenneth Casso...
move to common ALUHelpers for Logical test_pipe_caller.py
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commitdiff
2020-06-10
Luke Kenneth Casso...
move to common ALUHelpers for CR test_pipe_caller.py
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commitdiff
2020-06-10
Luke Kenneth Casso...
move to common ALUHelpers for branch test_pipe_caller.py
tree
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commitdiff
2020-06-10
Luke Kenneth Casso...
code-munge test_pipe_caller for ALU,
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commitdiff
2020-06-10
Jacob Lifshay
create div pipe setup stage
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commitdiff
2020-06-09
Luke Kenneth Casso...
correct local variable references
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commitdiff
2020-06-09
Luke Kenneth Casso...
bit more on TRAP handling (preparing priv instruction)
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commitdiff
2020-06-08
Luke Kenneth Casso...
add traptype and trapaddr to PowerDecoder2. idea is...
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commitdiff
2020-06-08
Luke Kenneth Casso...
add traptype and trapaddr to trap_input_data.py
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commitdiff
2020-06-08
Luke Kenneth Casso...
more verbose debug information tracking down SO/OV...
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commitdiff
2020-06-08
Luke Kenneth Casso...
set only the SO bit as sticky, not the OV flags as...
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commitdiff
2020-06-08
Luke Kenneth Casso...
clarify using microwatt calc_ov function.
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commitdiff
2020-06-08
Luke Kenneth Casso...
added check which shows that OV32 in "adde." is not...
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commitdiff
2020-06-08
Luke Kenneth Casso...
found section in 3.0B PDF that refers to "Program Inter...
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commitdiff
2020-06-08
Luke Kenneth Casso...
copy MSR into SRR1 in trap function
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commitdiff
2020-06-08
colepoirier
Fix spelling
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commitdiff
2020-06-07
Luke Kenneth Casso...
update trap with comments
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commitdiff
2020-06-07
colepoirier
Add TrapMainStage.trap() convenience function to set...
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commitdiff
2020-06-07
Luke Kenneth Casso...
add debug print statements, re-enable all tests in...
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commitdiff
2020-06-07
colepoirier
Add back test cases to cookie-cut from for fu/trap...
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commitdiff
2020-06-07
Luke Kenneth Casso...
add extra tests for mcrf: shows bug is not directly...
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commitdiff
2020-06-07
Luke Kenneth Casso...
add extra args to ISA in branch test_pipe_caller
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commitdiff
2020-06-07
Luke Kenneth Casso...
wark-wark, do not & rs[0] into carry-out from rotator
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commitdiff
2020-06-07
Luke Kenneth Casso...
update rotator.py to match microwatt rotator.vhdl
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commitdiff
2020-06-07
Luke Kenneth Casso...
add carry test to shift_rot test_pipe_caller: it fails...
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commitdiff
2020-06-07
Luke Kenneth Casso...
add extra args to ISA in test_pipe_caller.py
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commitdiff
2020-06-07
Luke Kenneth Casso...
add missing arg to ISA in test_compunit
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commitdiff
2020-06-07
Luke Kenneth Casso...
add extra missing args to ISA setup in alu test_pipe_caller
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commitdiff
2020-06-07
Luke Kenneth Casso...
add missing args to ISA
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commitdiff
2020-06-07
Luke Kenneth Casso...
add MSR to simulator context
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commitdiff
2020-06-07
Luke Kenneth Casso...
move MSR_PR checking to separate functiong
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commitdiff
2020-06-07
colepoirier
Fix missing 'comb +='
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commitdiff
2020-06-06
Luke Kenneth Casso...
experimenting with setting up and testing memory
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commitdiff
2020-06-06
Luke Kenneth Casso...
work out how to initialise memory directly
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commitdiff
2020-06-06
Luke Kenneth Casso...
initialise L0 Memory from simulator memory
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commitdiff
2020-06-06
Luke Kenneth Casso...
wait a little for wr.rel to activate if wrmask is active
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