git.libre-soc.org Git - soc.git/history - src/soc/interrupts/xics.py

[soc.git] / src / soc / interrupts / xics.py

2020-11-22	Luke Kenneth Casso...	simplify litex-core wishbone interfaces	blob \| commitdiff \| raw
2020-09-05	Luke Kenneth Casso...	hmmm XICS data being asserted on wb bus for too long	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	argh missed a VHDL "&" translating to Cat	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	reduce XICS address lookup by 2 bits	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	whoops, combinatorial loop on pending_priority	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	XICS addresses in words: divide by 4	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	move wb read/write to separate util test library and...	blob \| commitdiff \| raw \| diff to current
2020-09-04	Luke Kenneth Casso...	adding option to include XICS external interrupts.	blob \| commitdiff \| raw \| diff to current
2020-07-30	Luke Kenneth Casso...	ha! found source of XICS test bug: wishbone stb was...	blob \| commitdiff \| raw \| diff to current
2020-07-29	Luke Kenneth Casso...	more exploratory testing of XICS, joining ICP and ICS...	blob \| commitdiff \| raw \| diff to current
2020-07-29	Luke Kenneth Casso...	start on test joining XICS ICS to ICP	blob \| commitdiff \| raw \| diff to current
2020-07-29	Luke Kenneth Casso...	tidyup XICS, identify (potential?) bug?	blob \| commitdiff \| raw \| diff to current
2020-07-28	Luke Kenneth Casso...	add preliminary investigative test of XICS ICS	blob \| commitdiff \| raw \| diff to current
2020-07-27	Luke Kenneth Casso...	add 2nd part of XICS interrupt interface	blob \| commitdiff \| raw \| diff to current
2020-07-26	Luke Kenneth Casso...	start on conversion of xics.vhdl to nmigen	blob \| commitdiff \| raw \| diff to current

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