git.libre-soc.org Git - soc.git/history - src/soc/litex/florent/libresoc/core.py

[soc.git] / src / soc / litex / florent / libresoc / core.py

2020-10-03	Luke Kenneth Casso...	move iopad litex creation to ls180soc.py	blob \| commitdiff \| raw
2020-10-01	Luke Kenneth Casso...	add clksel, pll to ls180	blob \| commitdiff \| raw \| diff to current
2020-09-28	Luke Kenneth Casso...	lots of sorting out iopads	blob \| commitdiff \| raw \| diff to current
2020-09-26	Luke Kenneth Casso...	only enable pads connections for ls180 for now	blob \| commitdiff \| raw \| diff to current
2020-09-24	Luke Kenneth Casso...	enable GPIO pads through C4M JTAG	blob \| commitdiff \| raw \| diff to current
2020-09-24	Luke Kenneth Casso...	c4m iopad integration working	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	add jtagremote to litex sim, add new "variant" to core...	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	add jtag wishbone and jtag ports to libresoc litex...	blob \| commitdiff \| raw \| diff to current
2020-09-19	Luke Kenneth Casso...	add pc_o not connected	blob \| commitdiff \| raw \| diff to current
2020-09-19	Luke Kenneth Casso...	urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5	blob \| commitdiff \| raw \| diff to current
2020-09-19	Luke Kenneth Casso...	remove the gpio peripheral which was previously hard...	blob \| commitdiff \| raw \| diff to current
2020-09-19	Luke Kenneth Casso...	add 3x EINTs to ls180soc	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	move GPIO IRQ to 15 to match microwatt modifications	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	XICS addresses in words: divide by 4	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	increase wishbone address width to 29 for xics and...	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	add simple GPIO wishbone bus to litex sim.py	blob \| commitdiff \| raw \| diff to current
2020-09-04	Luke Kenneth Casso...	add XICS memory regions, shrink litex CSR memmap size...	blob \| commitdiff \| raw \| diff to current
2020-09-04	Luke Kenneth Casso...	adding XICS wb slave devices to litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-25	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-25	Luke Kenneth Casso...	add way to capture CR from DMI in litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-21	Luke Kenneth Casso...	get litex sim enabled with 32-bit wishbone bus	blob \| commitdiff \| raw \| diff to current
2020-08-05	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-08-05	Luke Kenneth Casso...	rename ibus/dbus (shorten)	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	add DMI debug interface to libresoc litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	more remove wildcard imports	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	adding litex sim experimentation.	blob \| commitdiff \| raw \| diff to current

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