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simplify litex-core wishbone interfaces
[soc.git]
/
src
/
soc
/
litex
/
florent
/
libresoc
/
core.py
2020-11-22
Luke Kenneth Casso...
simplify litex-core wishbone interfaces
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2020-11-14
Luke Kenneth Casso...
sigh, direction wrong in IOtypes litex core
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2020-11-13
Luke Kenneth Casso...
reduce clkcsel ls180 width (2 pins), rename pll_18...
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2020-11-13
Luke Kenneth Casso...
rename and add pll lock signal to ls180
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2020-11-13
Luke Kenneth Casso...
rename ls180 litex pll_48 output to pll_18
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2020-11-13
Luke Kenneth Casso...
remove io_in/out now it is not needed for niolib
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2020-11-06
Luke Kenneth Casso...
sigh sorting out litex pin-connections to sdram
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2020-10-21
Cole Poirier
versa_ecp5 adds ability to build and load for ulx3s85f...
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2020-10-15
Luke Kenneth Casso...
add extra variant to litex core
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2020-10-15
Luke Kenneth Casso...
disable gpio in litex core
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2020-10-15
Luke Kenneth Casso...
enable/disable litex irqs based on variant name
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2020-10-06
Luke Kenneth Casso...
add sdr bypass routing via JTAG boundary scan
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2020-10-04
Luke Kenneth Casso...
significant reorg of the litex pinspecs to use pinmux...
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2020-10-04
Luke Kenneth Casso...
remove ls180io import
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2020-10-03
Luke Kenneth Casso...
allow i2c to be routed via JTAG
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2020-10-03
Luke Kenneth Casso...
nope. put it back and connect to platform pads in...
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2020-10-03
Luke Kenneth Casso...
move iopad litex creation to ls180soc.py
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2020-10-01
Luke Kenneth Casso...
add clksel, pll to ls180
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2020-09-28
Luke Kenneth Casso...
lots of sorting out iopads
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2020-09-26
Luke Kenneth Casso...
only enable pads connections for ls180 for now
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2020-09-24
Luke Kenneth Casso...
enable GPIO pads through C4M JTAG
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2020-09-24
Luke Kenneth Casso...
c4m iopad integration working
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2020-09-22
Luke Kenneth Casso...
add jtagremote to litex sim, add new "variant" to core...
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2020-09-22
Luke Kenneth Casso...
add jtag wishbone and jtag ports to libresoc litex...
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2020-09-19
Luke Kenneth Casso...
add pc_o not connected
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2020-09-19
Luke Kenneth Casso...
urk. wishbone slave devices declared incorrectly (I...
semi_working_ecp5
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2020-09-19
Luke Kenneth Casso...
remove the gpio peripheral which was previously hard...
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2020-09-19
Luke Kenneth Casso...
add 3x EINTs to ls180soc
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2020-09-05
Luke Kenneth Casso...
move GPIO IRQ to 15 to match microwatt modifications
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2020-09-05
Luke Kenneth Casso...
XICS addresses in words: divide by 4
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2020-09-05
Luke Kenneth Casso...
increase wishbone address width to 29 for xics and...
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2020-09-05
Luke Kenneth Casso...
add simple GPIO wishbone bus to litex sim.py
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2020-09-04
Luke Kenneth Casso...
add XICS memory regions, shrink litex CSR memmap size...
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2020-09-04
Luke Kenneth Casso...
adding XICS wb slave devices to litex sim
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2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-25
Luke Kenneth Casso...
add way to capture CR from DMI in litex sim
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2020-08-21
Luke Kenneth Casso...
get litex sim enabled with 32-bit wishbone bus
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2020-08-05
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-05
Luke Kenneth Casso...
rename ibus/dbus (shorten)
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2020-08-04
Luke Kenneth Casso...
add DMI debug interface to libresoc litex sim
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2020-08-04
Luke Kenneth Casso...
more remove wildcard imports
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2020-08-04
Luke Kenneth Casso...
adding litex sim experimentation.
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