git.libre-soc.org Git - soc.git/history - src/soc/litex/florent/sim.py

[soc.git] / src / soc / litex / florent / sim.py

2020-09-02	Luke Kenneth Casso...	add bc ctr regression test when CTR=0 and CTR=1	blob \| commitdiff \| raw
2020-08-31	Luke Kenneth Casso...	add XER to fastregs and "construct" it in mfspr/mtspr	blob \| commitdiff \| raw \| diff to current
2020-08-30	Luke Kenneth Casso...	redo OP_CMP based on microwatt. L=1 had been ignored	blob \| commitdiff \| raw \| diff to current
2020-08-29	Luke Kenneth Casso...	break down XER into flags	blob \| commitdiff \| raw \| diff to current
2020-08-29	Luke Kenneth Casso...	add XER read via DMI interface to sim.py	blob \| commitdiff \| raw \| diff to current
2020-08-29	Luke Kenneth Casso...	investigating CR mtocrf / mfocrf	blob \| commitdiff \| raw \| diff to current
2020-08-25	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-25	Luke Kenneth Casso...	add way to capture CR from DMI in litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-24	Luke Kenneth Casso...	argh, reading regfile over DMI was overlapped and corru...	blob \| commitdiff \| raw \| diff to current
2020-08-24	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-23	Luke Kenneth Casso...	add algebraic ld tests lwax, lwaux	blob \| commitdiff \| raw \| diff to current
2020-08-23	Luke Kenneth Casso...	add in DMI "stat" loop which monitors core "stopping"	blob \| commitdiff \| raw \| diff to current
2020-08-23	Luke Kenneth Casso...	comment why litex sim mem map is altered	blob \| commitdiff \| raw \| diff to current
2020-08-22	Luke Kenneth Casso...	load bios not 1.bin unit test	blob \| commitdiff \| raw \| diff to current
2020-08-22	Luke Kenneth Casso...	add means to run microwatt test binaries	blob \| commitdiff \| raw \| diff to current
2020-08-22	Luke Kenneth Casso...	investigating litex sdrinit function	blob \| commitdiff \| raw \| diff to current
2020-08-21	Luke Kenneth Casso...	testing 64-bit wishbone bus after 32-bit still fails...	blob \| commitdiff \| raw \| diff to current
2020-08-21	Luke Kenneth Casso...	get litex sim enabled with 32-bit wishbone bus	blob \| commitdiff \| raw \| diff to current
2020-08-17	Luke Kenneth Casso...	move Mask to nmutil	blob \| commitdiff \| raw \| diff to current
2020-08-17	Luke Kenneth Casso...	use longer memtest in litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-16	Luke Kenneth Casso...	attempting to track down bug in litex bios memtest	blob \| commitdiff \| raw \| diff to current
2020-08-16	Luke Kenneth Casso...	limit debug reporting in litex sim to range of pc	blob \| commitdiff \| raw \| diff to current
2020-08-15	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-15	Luke Kenneth Casso...	thanks to daveshah, added simulation of dram	blob \| commitdiff \| raw \| diff to current
2020-08-05	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-05	Luke Kenneth Casso...	adding bus data width of 64 in litex sim doesnt work	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	cycle through INT regs, read and debug in litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	single-step and print out PC using DMI in litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	get litex sim to kick off a "STEP" via the DMI interfac...	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	connect up a DMI FSM to litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	more remove wildcard imports	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	do not use wildcard imports	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	adding litex sim experimentation.	blob \| commitdiff \| raw \| diff to current

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