replace PartitionedSignal with SimdSignal
[soc.git] / src / soc / litex /
9 days ago Luke Kenneth Casso... replace PartitionedSignal with SimdSignal master
11 days ago Luke Kenneth Casso... Merge branch 'pr' from nix-soc
2021-09-26 Las SafinAdd script for loading Libre-SOC onto Versa ECP5 board!
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-19 Las SafinAdd ppc64le cross compiler
2021-06-10 Luke Kenneth Casso... whoops Popcount datalen too big (wasted bits). reduce
2021-06-09 Luke Kenneth Casso... git submodule update
2021-06-09 Luke Kenneth Casso... disconnect pll clock, connected in peripheral interconnect
2021-06-03 Luke Kenneth Casso... no, do not assign clock to clock!
2021-05-26 Luke Kenneth Casso... remove err feature from sram4k wb
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway)
2021-05-24 Luke Kenneth Casso... change name of submodule to real_pll
2021-05-24 Luke Kenneth Casso... match up PLL names
2021-05-22 Luke Kenneth Casso... update submodule
2021-05-09 Luke Kenneth Casso... git submodule update
2021-04-23 Luke Kenneth Casso... submodule update
2021-04-18 Luke Kenneth Casso... give spblock512 a name as a submodule
2021-04-18 Luke Kenneth Casso... rename SPBlock_512W64B8W to lowercase
2021-04-18 Luke Kenneth Casso... submodule update
2021-04-18 Luke Kenneth Casso... submodule update
2021-04-18 Luke Kenneth Casso... submodule update
2021-04-16 Luke Kenneth Casso... submodule update
2021-04-08 Luke Kenneth Casso... submodule update
2021-04-06 Luke Kenneth Casso... git submodule update
2021-04-05 Luke Kenneth Casso... litex submodule update
2021-04-01 Luke Kenneth Casso... git submodule update
2021-04-01 Luke Kenneth Casso... add soc-cocotb-sim submodule
2021-04-01 Luke Kenneth Casso... submodule update
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Luke Kenneth Casso... corrections to Makefile for building / not-building...
2021-03-29 Luke Kenneth Casso... update submodule
2021-03-28 Luke Kenneth Casso... reduce regfile port usage on non-svp64
2021-03-22 Luke Kenneth Casso... add very small dff sram variant (no 4k SRAMs)
2021-03-13 Luke Kenneth Casso... include SVSTATE in namespace, passing to ISACaller
2021-03-12 Luke Kenneth Casso... remove old code
2021-03-12 Luke Kenneth Casso... remove old code
2021-03-12 Luke Kenneth Casso... remove old code
2021-03-06 Luke Kenneth Casso... add SPBlock_512W64B8W.v blackbox file
2021-03-05 Luke Kenneth Casso... remove sram4k wishbone bte/cti in litex interconnect
2021-02-20 Luke Kenneth Casso... add litex wishbone interconnect to 4x 4k SRAMs
2020-12-06 Luke Kenneth Casso... attempt to split into two separate GPIO banks due to...
2020-12-03 Luke Kenneth Casso... put ls180 litex bus width back to 32 bit temporarily
2020-12-03 Luke Kenneth Casso... argh issue with yosys ABC
2020-12-03 Luke Kenneth Casso... add 3 more 4k SRAMs, change WB bus width to 64 in ls180...
2020-11-22 Luke Kenneth Casso... simplify litex-core wishbone interfaces
2020-11-14 Luke Kenneth Casso... sigh, direction wrong in IOtypes litex core
2020-11-13 Luke Kenneth Casso... reduce number of nc in ls180 to 24
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180
2020-11-13 Luke Kenneth Casso... rename ls180 litex pll_48 output to pll_18
2020-11-13 Luke Kenneth Casso... remove io_in/out now it is not needed for niolib
2020-11-10 Luke Kenneth Casso... add build commands to Makefile for versa ecp5
2020-11-06 Luke Kenneth Casso... sigh sorting out litex pin-connections to sdram
2020-11-04 Luke Kenneth Casso... move back to 3.3v on X3 VERSA ECP5 connector
2020-11-03 Luke Kenneth Casso... swap jtag pinorder to match ulx3s
2020-11-03 Luke Kenneth Casso... change LVCMOS level on versa ecp5 jtag to 2.5v
2020-10-31 Cole Poirierversa_ecp5.py add 4 arbitrarily assigned gpio pins...
2020-10-30 Luke Kenneth Casso... add JTAG extension to versa_ecp5 then we can use it
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f...
2020-10-15 Luke Kenneth Casso... add commented-out connection to JTAG in ECP5 litex
2020-10-15 Luke Kenneth Casso... add extra variant to litex core
2020-10-15 Luke Kenneth Casso... syntax error
2020-10-15 Luke Kenneth Casso... disable gpio in litex core
2020-10-15 Luke Kenneth Casso... enable/disable litex irqs based on variant name
2020-10-12 Cole Poirierlitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5...
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for...
2020-10-11 Luke Kenneth Casso... record commands for building ECP5
2020-10-10 Cole Poirierflorent/versa_ecp5.py remove uneccessary imports, speci...
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-04 Luke Kenneth Casso... remove ls180io import
2020-10-04 Luke Kenneth Casso... move ls180io.py back into ls180.py
2020-10-03 Luke Kenneth Casso... allow i2c to be routed via JTAG
2020-10-03 Luke Kenneth Casso... nope. put it back and connect to platform pads in...
2020-10-03 Luke Kenneth Casso... move iopad litex creation to ls180soc.py
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180
2020-09-30 Luke Kenneth Casso... add I2C into ls180
2020-09-30 Luke Kenneth Casso... add ASIC version of I2C Master
2020-09-28 Luke Kenneth Casso... reduce not-connected IO pins
2020-09-28 Luke Kenneth Casso... connect SDRAM dqm to wrdata_mask
2020-09-28 Luke Kenneth Casso... lots of sorting out iopads
2020-09-28 Luke Kenneth Casso... rewrite ilang file after litex ls180 build
2020-09-27 Luke Kenneth Casso... add Makefile for creating ls180.il
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-26 Luke Kenneth Casso... try svf test of DMI MSR
2020-09-26 Luke Kenneth Casso... add ls180io.py
2020-09-26 Luke Kenneth Casso... get openocd svf test running, replicating jtag test
2020-09-26 Luke Kenneth Casso... add openocd configs
2020-09-26 Luke Kenneth Casso... reduce sdram pins to smaller address and only 1 cs_n
2020-09-26 Luke Kenneth Casso... only enable pads connections for ls180 for now
2020-09-24 Luke Kenneth Casso... do not have to use uart_litex gpio_litex names
2020-09-24 Luke Kenneth Casso... enable GPIO pads through C4M JTAG
2020-09-24 Luke Kenneth Casso... c4m iopad integration working
2020-09-23 Luke Kenneth Casso... cs_n and cke in sdram need to match in length
2020-09-23 Luke Kenneth Casso... change litex sdram pinouts to ASIC type
2020-09-23 Luke Kenneth Casso... redo litex SDCard to send out data/cmd o/i/en pins
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