add detection and disable of Instruction Wishbone based on JTAG command
[soc.git] / src / soc / minerva / units / fetch.py
2020-10-22 Luke Kenneth Casso... add detection and disable of Instruction Wishbone based...
2020-07-30 Luke Kenneth Casso... set sel line in minerva instruction fetch
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... sigh easier to just do a line-for-line comparison of...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... port minerva cache fixes
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... parameterise minerva i-cache
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... dewildcardify units
2020-03-11 Luke Kenneth Casso... add minerva source from https://github.com/lambdaconcep...