format code
[soc.git] / src / soc / minerva / units / loadstore.py
2020-07-22 Jacob Lifshayformat code
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... likewise cut across latest Minerva loadstore with line...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... port minerva cache fixes
2020-07-17 Luke Kenneth Casso... forward-port minerva loadstore bugfix
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-26 Luke Kenneth Casso... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth Casso... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... move comments to minerva LoadStoreInterface
2020-06-19 Luke Kenneth Casso... parameterise LoadStoreUnitInterface to be expandable
2020-06-15 Luke Kenneth Casso... whitespace cleanup, remove minerva DataSelector class
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... dewildcardify units
2020-03-11 Luke Kenneth Casso... add minerva source from https://github.com/lambdaconcep...