attempting to add SPRs to rfid test
[soc.git] / src / soc / minerva /
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... parameterise minerva i-cache
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth Casso... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... move comments to minerva LoadStoreInterface
2020-06-19 Luke Kenneth Casso... parameterise LoadStoreUnitInterface to be expandable
2020-06-15 Luke Kenneth Casso... start trying to fill in some comments in Minerva L1...
2020-06-15 Luke Kenneth Casso... whitespace cleanup
2020-06-15 Luke Kenneth Casso... imports and syntax errors fixed (found test_cache.py)
2020-06-15 Luke Kenneth Casso... more whitespace
2020-06-15 Luke Kenneth Casso... more whitespace on minerva (no unit tests, so cannot...
2020-06-15 Luke Kenneth Casso... whitespace cleanup, remove minerva DataSelector class
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-05-06 Luke Kenneth Casso... remove unneeded minerva code
2020-04-06 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-06 Jacob LifshayMerge branch 'fix-tests'
2020-04-06 Jacob Lifshayalmost all tests work
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... enable rvfi, fix imports
2020-03-11 Luke Kenneth Casso... destarify debug
2020-03-11 Luke Kenneth Casso... dewildcardify units
2020-03-11 Luke Kenneth Casso... dewildcardify unitsg
2020-03-11 Luke Kenneth Casso... sort out imports to get minerva generate working
2020-03-11 Luke Kenneth Casso... dewildcard core.py
2020-03-11 Luke Kenneth Casso... dewildcard cache.py
2020-03-11 Luke Kenneth Casso... dewildcard stage.py
2020-03-11 Luke Kenneth Casso... dewildcard wishbone.py
2020-03-11 Luke Kenneth Casso... replace isa import
2020-03-11 Luke Kenneth Casso... de-starify csr.py
2020-03-11 Luke Kenneth Casso... import minerva from soc.minerva
2020-03-11 Luke Kenneth Casso... add minerva source from https://github.com/lambdaconcep...