replace PartitionedSignal with SimdSignal
[soc.git] / src / soc / minerva /
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-05-14 Luke Kenneth Casso... remove minerva units previously missed in cleanout
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-05-04 Luke Kenneth Casso... remove minerva debug unit (not needed)
2021-05-04 Jonathan Neuschäferminerva tests: Don't import soc.minerva.csr
2020-11-22 Luke Kenneth Casso... simplify litex-core wishbone interfaces
2020-10-22 Luke Kenneth Casso... add detection and disable of Instruction Wishbone based...
2020-10-22 Luke Kenneth Casso... add detection and disable of LoadStore Wishbone based...
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-05 Luke Kenneth Casso... clear sel on loadstore
2020-07-30 Luke Kenneth Casso... set sel line in minerva instruction fetch
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... likewise cut across latest Minerva loadstore with line...
2020-07-17 Luke Kenneth Casso... sigh easier to just do a line-for-line comparison of...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... port minerva cache fixes
2020-07-17 Luke Kenneth Casso... forward-port minerva loadstore bugfix
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... parameterise minerva i-cache
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth Casso... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... move comments to minerva LoadStoreInterface
2020-06-19 Luke Kenneth Casso... parameterise LoadStoreUnitInterface to be expandable
2020-06-15 Luke Kenneth Casso... start trying to fill in some comments in Minerva L1...
2020-06-15 Luke Kenneth Casso... whitespace cleanup
2020-06-15 Luke Kenneth Casso... imports and syntax errors fixed (found test_cache.py)
2020-06-15 Luke Kenneth Casso... more whitespace
2020-06-15 Luke Kenneth Casso... more whitespace on minerva (no unit tests, so cannot...
2020-06-15 Luke Kenneth Casso... whitespace cleanup, remove minerva DataSelector class
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-05-06 Luke Kenneth Casso... remove unneeded minerva code
2020-04-06 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-06 Jacob LifshayMerge branch 'fix-tests'
2020-04-06 Jacob Lifshayalmost all tests work
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... fix more imports
2020-03-11 Luke Kenneth Casso... enable rvfi, fix imports
2020-03-11 Luke Kenneth Casso... destarify debug
2020-03-11 Luke Kenneth Casso... dewildcardify units
2020-03-11 Luke Kenneth Casso... dewildcardify unitsg
2020-03-11 Luke Kenneth Casso... sort out imports to get minerva generate working
2020-03-11 Luke Kenneth Casso... dewildcard core.py
2020-03-11 Luke Kenneth Casso... dewildcard cache.py
2020-03-11 Luke Kenneth Casso... dewildcard stage.py
2020-03-11 Luke Kenneth Casso... dewildcard wishbone.py
2020-03-11 Luke Kenneth Casso... replace isa import
2020-03-11 Luke Kenneth Casso... de-starify csr.py
2020-03-11 Luke Kenneth Casso... import minerva from soc.minerva
2020-03-11 Luke Kenneth Casso... add minerva source from https://github.com/lambdaconcep...