add SVSTATE to StateRegs
[soc.git] / src / soc / regfile / regfiles.py
2021-01-28 Luke Kenneth Casso... add SVSTATE to StateRegs
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth Casso... add DEC and TB to State regfile
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-14 Luke Kenneth Casso... put multi-ports back (for read) on int and fast regfiles
2020-08-13 Luke Kenneth Casso... sigh. convert Fast regfile to binary
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-13 Luke Kenneth Casso... create a RegFileMem class that uses Memory
2020-08-11 Luke Kenneth Casso... sigh, remove yet another int regfile read port
2020-08-11 Luke Kenneth Casso... reduce regfile port usage for INT and FAST
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports
2020-08-03 Luke Kenneth Casso... add extra port for debug read of int regs via DMI
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports
2020-07-14 Luke Kenneth Casso... add MSR reading to issue FSM
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support
2020-07-04 Luke Kenneth Casso... more rename spr1/spr2 to fast1/fast2
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM
2020-06-05 Luke Kenneth Casso... name regfile ports by name not numerical position
2020-06-05 Luke Kenneth Casso... whoops connecting up CR in wrong order. fixing with...
2020-06-05 Luke Kenneth Casso... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-04 Luke Kenneth Casso... initialise XER from simulation
2020-06-04 Luke Kenneth Casso... missing a fastregs write-port
2020-06-03 Luke Kenneth Casso... connect read-enable and src_i to regfile ports
2020-06-03 Luke Kenneth Casso... start putting a non-production core together,
2020-06-03 Luke Kenneth Casso... decide to elaborate Refiles *into* another class, rathe...
2020-06-03 Luke Kenneth Casso... turn RegFiles into module, add all regfiles to it
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... add class containing all regfiles
2020-06-02 Luke Kenneth Casso... whoops cut/paste error, creating write_ports not read_ports
2020-05-27 Luke Kenneth Casso... add extra INT regs port for now, add Fast Regfile
2020-05-27 Luke Kenneth Casso... added XER and CR regfiles, using new VirtualRegPort
2020-05-25 Luke Kenneth Casso... add INT, SPR and CR regfiles
2020-05-24 Luke Kenneth Casso... add stub regfiles.py