git.libre-soc.org Git - soc.git/history - src/soc/regfile/regfiles.py

[soc.git] / src / soc / regfile / regfiles.py

2020-07-14	Luke Kenneth Casso...	add MSR reading to issue FSM	blob \| commitdiff \| raw
2020-07-08	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-07-05	Luke Kenneth Casso...	add slow spr regfile regspec support	blob \| commitdiff \| raw \| diff to current
2020-07-04	Luke Kenneth Casso...	more rename spr1/spr2 to fast1/fast2	blob \| commitdiff \| raw \| diff to current
2020-06-18	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-06-18	Luke Kenneth Casso...	slightly hacky way to keep an eye on the PC	blob \| commitdiff \| raw \| diff to current
2020-06-16	Luke Kenneth Casso...	add test instruction memory SRAM	blob \| commitdiff \| raw \| diff to current
2020-06-05	Luke Kenneth Casso...	name regfile ports by name not numerical position	blob \| commitdiff \| raw \| diff to current
2020-06-05	Luke Kenneth Casso...	whoops connecting up CR in wrong order. fixing with...	blob \| commitdiff \| raw \| diff to current
2020-06-05	Luke Kenneth Casso...	fix syntax errors and use correct FastRegs (SRR0/1...	blob \| commitdiff \| raw \| diff to current
2020-06-04	Luke Kenneth Casso...	initialise XER from simulation	blob \| commitdiff \| raw \| diff to current
2020-06-04	Luke Kenneth Casso...	missing a fastregs write-port	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	connect read-enable and src_i to regfile ports	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	start putting a non-production core together,	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	decide to elaborate Refiles into another class, rathe...	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	turn RegFiles into module, add all regfiles to it	blob \| commitdiff \| raw \| diff to current
2020-06-03	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	add class containing all regfiles	blob \| commitdiff \| raw \| diff to current
2020-06-02	Luke Kenneth Casso...	whoops cut/paste error, creating write_ports not read_ports	blob \| commitdiff \| raw \| diff to current
2020-05-27	Luke Kenneth Casso...	add extra INT regs port for now, add Fast Regfile	blob \| commitdiff \| raw \| diff to current
2020-05-27	Luke Kenneth Casso...	added XER and CR regfiles, using new VirtualRegPort	blob \| commitdiff \| raw \| diff to current
2020-05-25	Luke Kenneth Casso...	add INT, SPR and CR regfiles	blob \| commitdiff \| raw \| diff to current
2020-05-24	Luke Kenneth Casso...	add stub regfiles.py	blob \| commitdiff \| raw \| diff to current

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