2022-02-27 |
Luke Kenneth Casso... | add XLEN option to regfiles via pspec |
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2022-01-19 |
Luke Kenneth Casso... | move DEC and TB into StateRegs, to make room in FastRegs |
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2022-01-18 |
Luke Kenneth Casso... | add support for DMI debug read of FAST Regfile SPRs |
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2022-01-04 |
Luke Kenneth Casso... | fix DriverConflict over MSR write in Issuer/Core by... |
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2021-12-23 |
Luke Kenneth Casso... | allow MSR reset to default to a value set by issuer_ver... |
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2021-11-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-29 |
Luke Kenneth Casso... | always set fwd_bus_mode=False on regfiles |
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2021-11-24 |
Luke Kenneth Casso... | convert hazard bitvectors to Reset-Priority SRLatch... |
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2021-11-24 |
Luke Kenneth Casso... | add 2nd hazard bitvector port for write-after-write |
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2021-11-21 |
Luke Kenneth Casso... | fixed issue with hazard dependencies, read will nott |
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2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-17 |
Luke Kenneth Casso... | core hazard bitvector regfiles need to be readable |
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2021-11-16 |
Luke Kenneth Casso... | use a virtual regfile port for the hazard bitvectors |
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2021-11-16 |
Luke Kenneth Casso... | create set/get ports for bitvectors |
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2021-11-16 |
Luke Kenneth Casso... | rename regports for bitvectors so that |
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2021-11-16 |
Luke Kenneth Casso... | whoops, hazard vectors were depth 1 width N |
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2021-11-11 |
Luke Kenneth Casso... | fix regfile port names for "fast" port access (regreduc... |
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2021-11-11 |
Luke Kenneth Casso... | add exact same number - and name - bitvector ports... |
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2021-11-11 |
Luke Kenneth Casso... | code-morph regfile port specs to a dictionary format... |
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2021-11-10 |
Luke Kenneth Casso... | morph regfiles to add hazard vector make_vecs function |
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2021-11-07 |
Luke Kenneth Casso... | add hazard vectors to Regfiles |
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2021-11-07 |
Luke Kenneth Casso... | add quick test of regfiles to output rtlil |
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2021-05-04 |
Luke Kenneth Casso... | add SVSTATE (SVSRR0) to TRAP pipeline |
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2021-05-04 |
Luke Kenneth Casso... | add SVSRR0 to FastRegsEnum |
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2021-04-27 |
Luke Kenneth Casso... | add option to disable bus forwarding on SPRs and FAST... |
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2021-04-27 |
Luke Kenneth Casso... | add option to enable/disable bus forwarding mode on... |
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2021-04-23 |
Luke Kenneth Casso... | move to import from openpower-isa for reg enums |
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2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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2021-03-30 |
Luke Kenneth Casso... | use port name for INT regfile to match up with test_run... |
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2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
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2021-03-28 |
Luke Kenneth Casso... | add option to reduce number of regfile ports (get DFFs... |
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2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
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2021-03-17 |
Luke Kenneth Casso... | add predication read ports (CR and INT) |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-14 |
Luke Kenneth Casso... | add Regfiles comments |
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2021-01-28 |
Luke Kenneth Casso... | add SVSTATE to StateRegs |
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2020-09-06 |
Luke Kenneth Casso... | minor code-munge on SPR-to-FAST mapping |
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2020-09-06 |
Luke Kenneth Casso... | move DEC and TB from StateRegs to FastRegs for several... |
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2020-09-06 |
Luke Kenneth Casso... | add DEC and TB to State regfile |
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2020-08-31 |
Luke Kenneth Casso... | add XER to fastregs and "construct" it in mfspr/mtspr |
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2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
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2020-08-14 |
Luke Kenneth Casso... | put multi-ports back (for read) on int and fast regfiles |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert Fast regfile to binary |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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2020-08-13 |
Luke Kenneth Casso... | create a RegFileMem class that uses Memory |
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2020-08-11 |
Luke Kenneth Casso... | sigh, remove yet another int regfile read port |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile port usage for INT and FAST |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile ports by creating separate STATE regfile |
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2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
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2020-08-03 |
Luke Kenneth Casso... | add extra port for debug read of int regs via DMI |
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2020-07-22 |
Luke Kenneth Casso... | reduce number of FastRegs read ports |
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2020-07-14 |
Luke Kenneth Casso... | add MSR reading to issue FSM |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-05 |
Luke Kenneth Casso... | add slow spr regfile regspec support |
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2020-07-04 |
Luke Kenneth Casso... | more rename spr1/spr2 to fast1/fast2 |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Luke Kenneth Casso... | slightly hacky way to keep an eye on the PC |
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2020-06-16 |
Luke Kenneth Casso... | add test instruction memory SRAM |
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2020-06-05 |
Luke Kenneth Casso... | name regfile ports by name not numerical position |
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2020-06-05 |
Luke Kenneth Casso... | whoops connecting up CR in wrong order. fixing with... |
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2020-06-05 |
Luke Kenneth Casso... | fix syntax errors and use correct FastRegs (SRR0/1... |
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2020-06-04 |
Luke Kenneth Casso... | initialise XER from simulation |
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2020-06-04 |
Luke Kenneth Casso... | missing a fastregs write-port |
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2020-06-03 |
Luke Kenneth Casso... | connect read-enable and src_i to regfile ports |
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2020-06-03 |
Luke Kenneth Casso... | start putting a non-production core together, |
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2020-06-03 |
Luke Kenneth Casso... | decide to elaborate Refiles *into* another class, rathe... |
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2020-06-03 |
Luke Kenneth Casso... | turn RegFiles into module, add all regfiles to it |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-03 |
Luke Kenneth Casso... | add class containing all regfiles |
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2020-06-02 |
Luke Kenneth Casso... | whoops cut/paste error, creating write_ports not read_ports |
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2020-05-27 |
Luke Kenneth Casso... | add extra INT regs port for now, add Fast Regfile |
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2020-05-27 |
Luke Kenneth Casso... | added XER and CR regfiles, using new VirtualRegPort |
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2020-05-25 |
Luke Kenneth Casso... | add INT, SPR and CR regfiles |
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2020-05-24 |
Luke Kenneth Casso... | add stub regfiles.py |
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