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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / regfile / sram_wrapper.py
2022-04-30 Cesar StraussImplement transparent read port option on the XOR wrapp... commit | commitdiff
2022-04-28 Cesar StraussTest simultaneous transparent reads and partial writes commit | commitdiff
2022-04-17 Cesar StraussImplement a 1W/1R register file, XOR style commit | commitdiff
2022-04-17 Cesar StraussFormal proof of pseudo 1W/2R SRAM commit | commitdiff
2022-04-17 Cesar StraussAdd transparent option for the full read port commit | commitdiff
2022-04-17 Cesar StraussImplement a pseudo 1W/2R memory commit | commitdiff
2022-04-16 Cesar StraussCheck non-transparent 1W/1R SRAM wrapper commit | commitdiff
2022-04-16 Cesar StraussEnable read port for non-transparent memories commit | commitdiff
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc commit | commitdiff
2022-04-16 Cesar StraussAdd port declarations to the SRAM wrappers commit | commitdiff
2022-04-16 Cesar StraussChange write lane signal from one-hot to binary commit | commitdiff
2022-04-16 Cesar StraussSynchronize LVT state, completing the induction proof commit | commitdiff
2022-04-16 Cesar StraussSync proof state with downstream memories commit | commitdiff
2022-04-15 Cesar StraussComplete moving the induction support into the DUT commit | commitdiff
2022-04-15 Cesar StraussFix incorrect signal widths commit | commitdiff
2022-04-15 Cesar StraussMove part of formal proof to the implementation commit | commitdiff
2022-04-10 Cesar StraussBegin a formal proof of the LVT-based 1W/1R wrapper commit | commitdiff
2022-04-10 Cesar StraussImplement 1W/1R with a transparent (or not) read port. commit | commitdiff
2022-04-10 Cesar StraussImplement a true 1W/1R memory from 1RW blocks commit | commitdiff
2022-04-03 Luke Kenneth Casso... cant stand the practice of putting docstrings *after... commit | commitdiff
2022-04-03 Cesar StraussExtend the proof to a non-transparent port commit | commitdiff
2022-04-03 Cesar StraussRun formal proof on both types (even/odd) of phased... commit | commitdiff
2022-04-03 Cesar StraussComplete the formal proof of the pseudo dual port SRAM commit | commitdiff
2022-04-03 Cesar StraussImplement a debug port on the pseudo 1W/1R SRAM commit | commitdiff
2022-04-03 Cesar StraussFormal proof of the phased write dual port memory wrapper commit | commitdiff
2022-04-02 Cesar StraussImplement transparent read ports on the phased write... commit | commitdiff
2022-04-02 Cesar StraussImplement and test a "phased write port" memory commit | commitdiff
2022-03-27 Cesar StraussFinish the SRAM formal proof by implementing induction commit | commitdiff
2022-03-26 Cesar StraussAdd formal verification of the single port memory block commit | commitdiff
2022-03-13 Cesar StraussSimulate some read/write/modify operations on the SRAM... commit | commitdiff
2022-03-13 Cesar StraussAdd a Single R/W Port SRAM model commit | commitdiff