Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / regfile / util.py
2021-05-04 Luke Kenneth Casso... missed that soc.regfile.util has moved to openpower...
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2020-09-06 Luke Kenneth Casso... add unit test for slow SPRs (SPRG0/1)
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... sorting out setting of XER
2020-07-08 Luke Kenneth Casso... add spr to fast reg converter
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR