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radix: reading first page table entry
[soc.git]
/
src
/
soc
/
regfile
/
virtual_port.py
2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-25
Luke Kenneth Casso...
add CR read to DMI interface
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-05-26
Luke Kenneth Casso...
check assertions
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2020-05-26
Luke Kenneth Casso...
make read/write regs properly internal
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2020-05-26
Luke Kenneth Casso...
add VirtualRegPort test, seems to demonstrate it working
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2020-05-26
Luke Kenneth Casso...
remove sync (not needed)
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2020-05-26
Luke Kenneth Casso...
redo focus of virtual reg port to do only full datawidt...
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2020-05-26
Luke Kenneth Casso...
sort-of (maybe) implemented a virtual port on top of...
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2020-05-26
Luke Kenneth Casso...
try new variant of VirtualRegFile
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2020-05-26
Luke Kenneth Casso...
continue virtual regfile port
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2020-05-26
colepoirier
First attempt at implementing block access rd and wr...
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