Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / regfile / virtual_port.py
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Luke Kenneth Casso... core hazard bitvector regfiles need to be readable
2021-11-16 Luke Kenneth Casso... use a virtual regfile port for the hazard bitvectors
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-05-26 Luke Kenneth Casso... check assertions
2020-05-26 Luke Kenneth Casso... make read/write regs properly internal
2020-05-26 Luke Kenneth Casso... add VirtualRegPort test, seems to demonstrate it working
2020-05-26 Luke Kenneth Casso... remove sync (not needed)
2020-05-26 Luke Kenneth Casso... redo focus of virtual reg port to do only full datawidt...
2020-05-26 Luke Kenneth Casso... sort-of (maybe) implemented a virtual port on top of...
2020-05-26 Luke Kenneth Casso... try new variant of VirtualRegFile
2020-05-26 Luke Kenneth Casso... continue virtual regfile port
2020-05-26 colepoirierFirst attempt at implementing block access rd and wr...