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remove ClockSelect module, use DummyPLL
[soc.git] / src / soc / regfile /
2020-09-06 Luke Kenneth Casso... add reset option to Register tree | commitdiff
2020-09-06 Luke Kenneth Casso... add unit test for slow SPRs (SPRG0/1) tree | commitdiff
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping tree | commitdiff
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several... tree | commitdiff
2020-09-06 Luke Kenneth Casso... add DEC and TB to State regfile tree | commitdiff
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface tree | commitdiff
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and... tree | commitdiff
2020-08-14 Luke Kenneth Casso... put multi-ports back (for read) on int and fast regfiles tree | commitdiff
2020-08-13 Luke Kenneth Casso... add forwarding-bus mode to Regfile Memory (and disable it) tree | commitdiff
2020-08-13 Luke Kenneth Casso... sigh. convert Fast regfile to binary tree | commitdiff
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing tree | commitdiff
2020-08-13 Luke Kenneth Casso... create a RegFileMem class that uses Memory tree | commitdiff
2020-08-11 Luke Kenneth Casso... sigh, remove yet another int regfile read port tree | commitdiff
2020-08-11 Luke Kenneth Casso... reduce regfile port usage for INT and FAST tree | commitdiff
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile tree | commitdiff
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports tree | commitdiff
2020-08-03 Luke Kenneth Casso... add extra port for debug read of int regs via DMI tree | commitdiff
2020-07-29 Jacob Lifshayadd __init__.py to all source directories tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Jacob Lifshayformat code tree | commitdiff
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports tree | commitdiff
2020-07-14 Luke Kenneth Casso... add MSR reading to issue FSM tree | commitdiff
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup tree | commitdiff
2020-07-08 Luke Kenneth Casso... sorting out setting of XER tree | commitdiff
2020-07-08 Luke Kenneth Casso... add spr to fast reg converter tree | commitdiff
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support tree | commitdiff
2020-07-04 Luke Kenneth Casso... more rename spr1/spr2 to fast1/fast2 tree | commitdiff
2020-07-04 Luke Kenneth Casso... add gitignores tree | commitdiff
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast) tree | commitdiff
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC tree | commitdiff
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM tree | commitdiff
2020-06-05 Luke Kenneth Casso... name regfile ports by name not numerical position tree | commitdiff
2020-06-05 Luke Kenneth Casso... whoops connecting up CR in wrong order. fixing with... tree | commitdiff
2020-06-05 Luke Kenneth Casso... fix syntax errors and use correct FastRegs (SRR0/1... tree | commitdiff
2020-06-04 Luke Kenneth Casso... initialise XER from simulation tree | commitdiff
2020-06-04 Luke Kenneth Casso... add extra argument (not used) to regfile.py tree | commitdiff
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase tree | commitdiff
2020-06-04 Luke Kenneth Casso... missing a fastregs write-port tree | commitdiff
2020-06-03 Luke Kenneth Casso... connect read-enable and src_i to regfile ports tree | commitdiff
2020-06-03 Luke Kenneth Casso... start putting a non-production core together, tree | commitdiff
2020-06-03 Luke Kenneth Casso... decide to elaborate Refiles *into* another class, rathe... tree | commitdiff
2020-06-03 Luke Kenneth Casso... turn RegFiles into module, add all regfiles to it tree | commitdiff
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-06-03 Luke Kenneth Casso... add class containing all regfiles tree | commitdiff
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR tree | commitdiff
2020-06-02 Luke Kenneth Casso... whoops cut/paste error, creating write_ports not read_ports tree | commitdiff
2020-06-01 Michael NolanAdd proof for RegFile tree | commitdiff
2020-06-01 Michael NolanAdd proof for RegFileArray tree | commitdiff
2020-06-01 Michael NolanHave regfile use AnySeq instead of AnyConst tree | commitdiff
2020-06-01 Michael NolanEnable k-induction for register file proof tree | commitdiff
2020-06-01 Michael NolanThat was weird. For some reason it wasn't generating... tree | commitdiff
2020-06-01 Michael NolanFull BMC proof of Register tree | commitdiff
2020-06-01 Michael NolanBegin rewrite of proof_regfile.py tree | commitdiff
2020-05-29 Luke Kenneth Casso... interesting. use of Settle() works, showing that Regfi... tree | commitdiff
2020-05-28 Luke Kenneth Casso... messing about with proof_regfile.py tree | commitdiff
2020-05-28 colepoirierAdded Initial() synchronous check with draft truth tree | commitdiff
2020-05-28 Luke Kenneth Casso... hmm.... tree | commitdiff
2020-05-28 colepoirierAdd sync Assert for _wrports 'wen' signal in proof_regf... tree | commitdiff
2020-05-27 Luke Kenneth Casso... do not use range(0, x) - just range(x) tree | commitdiff
2020-05-27 Luke Kenneth Casso... remove write-block on register zero tree | commitdiff
2020-05-27 colepoirierDerive proof_regfile Driver from regfile.Register(... tree | commitdiff
2020-05-27 colepoirierFix indentation of regfile/formal/proof_regfile.py tree | commitdiff
2020-05-27 colepoirierFirst commit of proof of regfile, not working yet tree | commitdiff
2020-05-27 Luke Kenneth Casso... add extra INT regs port for now, add Fast Regfile tree | commitdiff
2020-05-27 Luke Kenneth Casso... added XER and CR regfiles, using new VirtualRegPort tree | commitdiff
2020-05-26 Luke Kenneth Casso... check assertions tree | commitdiff
2020-05-26 Luke Kenneth Casso... make read/write regs properly internal tree | commitdiff
2020-05-26 Luke Kenneth Casso... add VirtualRegPort test, seems to demonstrate it working tree | commitdiff
2020-05-26 Luke Kenneth Casso... remove sync (not needed) tree | commitdiff
2020-05-26 Luke Kenneth Casso... get score6600_multi.py working again tree | commitdiff
2020-05-26 Luke Kenneth Casso... redo focus of virtual reg port to do only full datawidt... tree | commitdiff
2020-05-26 Luke Kenneth Casso... sort-of (maybe) implemented a virtual port on top of... tree | commitdiff
2020-05-26 Luke Kenneth Casso... try new variant of VirtualRegFile tree | commitdiff
2020-05-26 Luke Kenneth Casso... use nmutil treereduce tree | commitdiff
2020-05-26 Luke Kenneth Casso... continue virtual regfile port tree | commitdiff
2020-05-26 colepoirierFirst attempt at implementing block access rd and wr... tree | commitdiff
2020-05-25 Luke Kenneth Casso... correct links in regfile docstring tree | commitdiff
2020-05-25 Luke Kenneth Casso... document regfiles tree | commitdiff
2020-05-25 Luke Kenneth Casso... add INT, SPR and CR regfiles tree | commitdiff
2020-05-24 Luke Kenneth Casso... add stub regfiles.py tree | commitdiff
2020-03-09 Luke Kenneth Casso... move all source directories to soc so that "import... tree | commitdiff