Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / simple / issuer.py
2022-07-06 Luke Kenneth Casso... update pinmux submodule, rename to "fabric"
2022-07-06 Luke Kenneth Casso... add fabric compatibility mode
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious...
2022-04-16 Tobias Platenpart two of issuer_fix: read pspec.microwatt_old and...
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc
2022-04-16 Luke Kenneth Casso... put the old microwatt compatibility back
2022-04-16 Luke Kenneth Casso... blegh.
2022-04-12 Tobias Platenissuer.py: add microwatt_old and microwatt_debug options
2022-04-09 Luke Kenneth Casso... add a new make target for setting coldboot firmware...
2022-03-12 Luke Kenneth Casso... introduce extra register of delay to split combinatoria...
2022-03-12 Luke Kenneth Casso... Revert "store cur_state.pc+4 in separate register to...
2022-03-12 Luke Kenneth Casso... store cur_state.pc+4 in separate register to help reduce
2022-02-28 Luke Kenneth Casso... attempting to introduce an extra few clock cycles delay...
2022-02-20 Luke Kenneth Casso... put LDST go-store on a 1-clock delay to help with combi...
2022-01-21 Luke Kenneth Casso... sigh, monitor DEC/TB StateRegs "properly" so that the...
2022-01-19 Luke Kenneth Casso... move DEC and TB into StateRegs, to make room in FastRegs
2022-01-18 Luke Kenneth Casso... add support for DMI debug read of FAST Regfile SPRs
2022-01-17 Luke Kenneth Casso... connect up DEC/TB FSM pauser from core to Issuer
2022-01-17 Luke Kenneth Casso... comments
2022-01-17 Luke Kenneth Casso... whitespace
2022-01-17 Luke Kenneth Casso... add signal for pausing the DEC/TB FSM to IssuerBase
2022-01-09 Luke Kenneth Casso... grab the LDST request address for microwatt verilator...
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error:
2022-01-07 Luke Kenneth Casso... add msr_o to issuer in microwatt_compat mode
2022-01-05 Luke Kenneth Casso... add easy-to-access debug reporting of instruction and PC
2022-01-04 Luke Kenneth Casso... fix DriverConflict over MSR write in Issuer/Core by...
2022-01-04 Luke Kenneth Casso... remove FetchFSM from TestIssuer (it served its purpose...
2022-01-03 Luke Kenneth Casso... doh, bus-hack was the wrong way round. *output* the...
2022-01-03 Luke Kenneth Casso... sigh, microwatts wishbone bus usage is non-wishbone...
2022-01-03 Luke Kenneth Casso... sigh have to allow external clocks and reset mess even...
2022-01-03 Luke Kenneth Casso... add missing ext_irq signal to testissuer in microwatt...
2022-01-03 Luke Kenneth Casso... adding an extra option to issuer_verilog.py to be able...
2022-01-03 Luke Kenneth Casso... bring external irq out for microwatt-compatible mode...
2021-12-28 Cesar StraussAdd an --inorder option to test_issuer.py
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute.
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped.
2021-12-22 Luke Kenneth Casso... fix issues with running core in DMI "stopped" status...
2021-12-22 Luke Kenneth Casso... whoops, use MSR.IR for I-Cache fetch!
2021-12-21 Luke Kenneth Casso... continue to assert PC in FetchFSM if needed
2021-12-21 Luke Kenneth Casso... for each unit test case in test_issuer_mmu_data_path...
2021-12-19 Luke Kenneth Casso... add hard stop address in ifetch unit test, bit of a...
2021-12-19 Luke Kenneth Casso... set terminate if core terminate requested
2021-12-19 Luke Kenneth Casso... add DMI STOPADDR register and use it in HDLRunner to...
2021-12-18 Luke Kenneth Casso... sort out reset signalling after tracking down Simulatio...
2021-12-18 Luke Kenneth Casso... add icache/dcache/mmu unit test for TestIssuer
2021-12-18 Luke Kenneth Casso... get instructions to re-run in issuer after I-Cache...
2021-12-16 Luke Kenneth Casso... whoops remove duplicate code (cut/paste error) no harm...
2021-12-15 Luke Kenneth Casso... read MSR.PR and MSR.DR and update ICache priv/virt...
2021-12-15 Luke Kenneth Casso... move update of pc, msr and svstate into TestIssuerBase
2021-12-15 Luke Kenneth Casso... comment-out TestIssuerInternalInorder for now
2021-12-15 Luke Kenneth Casso... move alternative TestIssuerInternalInOrder to new file
2021-12-15 Luke Kenneth Casso... split out common elaboratable code from TestIssuer,
2021-12-15 Luke Kenneth Casso... big split-out of common functions in TestIssuer to...
2021-12-15 Luke Kenneth Casso... simplifying / tidyup of TestIssuer to get CoreState
2021-12-15 Luke Kenneth Casso... sort out MSR, read/write in same way as PC/SVSTATE...
2021-12-15 Luke Kenneth Casso... get fetch_failed working with no MMU
2021-12-14 Luke Kenneth Casso... trying to get TestIssuer FSM to respond correctly to...
2021-12-13 Luke Kenneth Casso... request a flush of icache to clear the instruction...
2021-12-12 Luke Kenneth Casso... set and reset instruction fault so it does not occur...
2021-12-12 Luke Kenneth Casso... when an exception happens, if it is a fetch_failed...
2021-12-12 Luke Kenneth Casso... drat, a test inverting the instruction made it into...
2021-12-12 Luke Kenneth Casso... starting to hack in fetch failed (including OP_FETCH_FA...
2021-12-12 Luke Kenneth Casso... set fetch_failed into PowerDecoder2 combinatorially
2021-12-12 Luke Kenneth Casso... in a terrible botched way, get at I-Cache and set it up
2021-12-09 Luke Kenneth Casso... wire fetch_failed from I-Cache to PowerDecoder2
2021-12-09 Jacob Lifshayformat code
2021-11-23 Luke Kenneth Casso... more comments
2021-11-22 Luke Kenneth Casso... make FetchFSM take PC as an input in its ispec
2021-11-22 Luke Kenneth Casso... local variable rename in FetchFSM
2021-11-22 Luke Kenneth Casso... split out FetchFSM into separate module
2021-11-21 Luke Kenneth Casso... reset execute back to ISSUE_START if at INSN_WAIT and
2021-11-21 Luke Kenneth Casso... complex. TestRunner now does not work properly unless...
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-18 Luke Kenneth Casso... experimenting with overlapping instructions, bit of...
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Luke Kenneth Casso... make core busy_o part of the CoreOutput data structure
2021-11-08 Luke Kenneth Casso... remove unused variable
2021-11-08 Luke Kenneth Casso... remove issue_i from core, use i_valid instead to decide...
2021-11-08 Luke Kenneth Casso... move "exception happened" detection from TestIssuer...
2021-11-08 Luke Kenneth Casso... use p.i_valid in core instead of explicit signal ivalid_i
2021-11-08 Luke Kenneth Casso... use Pipeline API o_ready instead of explicit core busy_...
2021-11-08 Luke Kenneth Casso... move simple core input and output data to in/out data...
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-10 Luke Kenneth Casso... update explanatory comments on LD/ST exception handling
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-08-29 Luke Kenneth Casso... unnecessary signal rename ivalid_i to ii_valid (reverting)
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-07-12 Luke Kenneth Casso... use default decoder, do not pass one in.
2021-06-24 Luke Kenneth Casso... propagate new use_svp64_ldst_dec mode through TestCore...
2021-06-24 Luke Kenneth Casso... add an explicit PowerDecoder.is_svp64_mode flag to...
2021-06-09 Luke Kenneth Casso... disconnect pll clock, connected in peripheral interconnect
2021-06-09 Luke Kenneth Casso... add in/out of ref_clk and pllclk_clk when PLL enabled
2021-06-03 Luke Kenneth Casso... comment out domains that have already been created
2021-06-03 Luke Kenneth Casso... no, do not assign clock to clock!
2021-06-03 Luke Kenneth Casso... sort out PLL domains but bypass PLL due to lack of...
2021-06-03 Luke Kenneth Casso... use DomainRenamer on all sub-components of TestIssuer
2021-06-03 Luke Kenneth Casso... make core_rst a member of TestIssuerInternal
2021-05-27 Luke Kenneth Casso... adjust PLL connections looking for coriolis2 issue
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