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add MSR reading to issue FSM
[soc.git]
/
src
/
soc
/
simple
/
issuer.py
2020-07-14
Luke Kenneth Casso...
add MSR reading to issue FSM
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-12
Luke Kenneth Casso...
exit FSM when termination detected
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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2020-07-07
Luke Kenneth Casso...
add core start/stop capability, and OP_ATTN support
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2020-07-06
Luke Kenneth Casso...
add mul unit to test_issuer
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2020-07-05
Luke Kenneth Casso...
add slow spr regfile regspec support
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2020-07-02
Luke Kenneth Casso...
allow flexible selection of the types of ALUs
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2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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2020-07-02
Luke Kenneth Casso...
use single-arg pspec for TestIssuer and Core
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2020-07-01
Luke Kenneth Casso...
add name "test_issuer" to ilang conversion
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2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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2020-06-28
Luke Kenneth Casso...
expand instruction bus width to 64 bit, start on a...
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2020-06-27
Luke Kenneth Casso...
make PortInterface modules consistent with same API
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2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-18
Luke Kenneth Casso...
got loop example operational by noting when PC fastreg...
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2020-06-18
Luke Kenneth Casso...
slightly hacky way to keep an eye on the PC
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2020-06-17
Luke Kenneth Casso...
split out TestIssuer into separate module
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