git.libre-soc.org Git - soc.git/history - src/soc/simple/issuer.py

[soc.git] / src / soc / simple / issuer.py

2020-10-07	Luke Kenneth Casso...	reorder / reorganise reset signals slightly	blob \| commitdiff \| raw
2020-10-06	Luke Kenneth Casso...	add sdr bypass routing via JTAG boundary scan	blob \| commitdiff \| raw \| diff to current
2020-10-04	Luke Kenneth Casso...	significant reorg of the litex pinspecs to use pinmux...	blob \| commitdiff \| raw \| diff to current
2020-10-03	Luke Kenneth Casso...	minor reorg on JTAG, allow alternative pinset dict...	blob \| commitdiff \| raw \| diff to current
2020-10-01	Luke Kenneth Casso...	add clksel, pll to ls180	blob \| commitdiff \| raw \| diff to current
2020-10-01	Luke Kenneth Casso...	create dummy PLL block, connect up to core and clock...	blob \| commitdiff \| raw \| diff to current
2020-09-26	Luke Kenneth Casso...	DMI-to-JTAG needed to be "sync" to get ack/resp right	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	move dmi_sim to separate module	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	add jtag interface to issuer_verilog	blob \| commitdiff \| raw \| diff to current
2020-09-08	Luke Kenneth Casso...	create a special subset of Decoder Record for storing...	blob \| commitdiff \| raw \| diff to current
2020-09-08	Luke Kenneth Casso...	pass in state into PowerDecode2, save on eqs and wires	blob \| commitdiff \| raw \| diff to current
2020-09-07	Luke Kenneth Casso...	add per-FU PowerDecoders. should now be subsettable	blob \| commitdiff \| raw \| diff to current
2020-09-06	Luke Kenneth Casso...	copy dec SPR into decoder cur_state	blob \| commitdiff \| raw \| diff to current
2020-09-06	Luke Kenneth Casso...	wark-wark, fast regs is binary-addressed	blob \| commitdiff \| raw \| diff to current
2020-09-06	Luke Kenneth Casso...	add comments for DEC / TB	blob \| commitdiff \| raw \| diff to current
2020-09-06	Luke Kenneth Casso...	add a DEC/TB FSM to TestIssuer	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	add comments on MSR read	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	move GPIO IRQ to 15 to match microwatt modifications	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	MSR read in INSN_READ only occurs for 1 cycle	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	sync on ICP eint	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	connect XICS core irq to Decode2 eint	blob \| commitdiff \| raw \| diff to current
2020-09-05	Luke Kenneth Casso...	add simple GPIO peripheral to verilog TestIssuer	blob \| commitdiff \| raw \| diff to current
2020-09-04	Luke Kenneth Casso...	bring out XICS ICS interrupt levels so that they can...	blob \| commitdiff \| raw \| diff to current
2020-09-04	Luke Kenneth Casso...	adding option to include XICS external interrupts.	blob \| commitdiff \| raw \| diff to current
2020-08-29	Luke Kenneth Casso...	add XER read via DMI interface to sim.py	blob \| commitdiff \| raw \| diff to current
2020-08-29	Luke Kenneth Casso...	add hack to get at XER through DMI interface	blob \| commitdiff \| raw \| diff to current
2020-08-25	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-25	Luke Kenneth Casso...	add CR read to DMI interface	blob \| commitdiff \| raw \| diff to current
2020-08-24	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-23	Luke Kenneth Casso...	bring "core stopped" signal out through DMI interface	blob \| commitdiff \| raw \| diff to current
2020-08-21	Luke Kenneth Casso...	get litex sim enabled with 32-bit wishbone bus	blob \| commitdiff \| raw \| diff to current
2020-08-16	Luke Kenneth Casso...	read delay on getting regfile data	blob \| commitdiff \| raw \| diff to current
2020-08-15	Luke Kenneth Casso...	rather big change to interaction between regfile and...	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	ha! "state" (pc, msr) not properly passed to core	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	drop in insn_state synchronously in issuer, at same...	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	finally, fix decoder combinatorial loop	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	sync up the core decode-execute state,	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	move instruction decoder out of core	blob \| commitdiff \| raw \| diff to current
2020-08-14	Luke Kenneth Casso...	sort out instruction stop/cancel when adding a new...	blob \| commitdiff \| raw \| diff to current
2020-08-13	Luke Kenneth Casso...	fix dmi reg read	blob \| commitdiff \| raw \| diff to current
2020-08-13	Luke Kenneth Casso...	sync on pc writing when changed	blob \| commitdiff \| raw \| diff to current
2020-08-13	Luke Kenneth Casso...	sigh. convert INT regfile to binary addressing	blob \| commitdiff \| raw \| diff to current
2020-08-11	Luke Kenneth Casso...	reduce regfile ports by creating separate STATE regfile	blob \| commitdiff \| raw \| diff to current
2020-08-11	Luke Kenneth Casso...	reducing regfile port usage by sharing read ports	blob \| commitdiff \| raw \| diff to current
2020-08-10	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-09	Luke Kenneth Casso...	fix combinatorial loop in ldst compunit	blob \| commitdiff \| raw \| diff to current
2020-08-09	Luke Kenneth Casso...	use rising edge detection on st go_i/rel_o	blob \| commitdiff \| raw \| diff to current
2020-08-09	Luke Kenneth Casso...	get rid of MSR read combinatorial loop	blob \| commitdiff \| raw \| diff to current
2020-08-09	Luke Kenneth Casso...	delay go_st by one cycle, break combinatorial loop	blob \| commitdiff \| raw \| diff to current
2020-08-05	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-05	Luke Kenneth Casso...	add div FSM as default for test_issuer in verilog and...	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	read/set pc outside of FSM so that DMI interface can...	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	whoops must output NIA not PC to debug DMI query in...	blob \| commitdiff \| raw \| diff to current
2020-08-04	Luke Kenneth Casso...	add DMI debug interface to libresoc litex sim	blob \| commitdiff \| raw \| diff to current
2020-08-03	Luke Kenneth Casso...	add quick demo/test of reading DMI reg 9	blob \| commitdiff \| raw \| diff to current
2020-08-03	Luke Kenneth Casso...	pass state (MSR/PC) around between PowerDecode2, DMI...	blob \| commitdiff \| raw \| diff to current
2020-08-03	Luke Kenneth Casso...	use new soc.config.state CoreState class in DMI and...	blob \| commitdiff \| raw \| diff to current
2020-08-03	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-08-03	Luke Kenneth Casso...	change over to DMI debug start/stop interface	blob \| commitdiff \| raw \| diff to current
2020-07-31	Luke Kenneth Casso...	restrict external port list further in test_issuer	blob \| commitdiff \| raw \| diff to current
2020-07-30	Luke Kenneth Casso...	core_start/stop/endian were inverted (output)	blob \| commitdiff \| raw \| diff to current
2020-07-30	Luke Kenneth Casso...	ha! have to explicitly specify the ports when writing...	blob \| commitdiff \| raw \| diff to current
2020-07-29	Luke Kenneth Casso...	bit of a big change: add prefixes "cu_" to all CompUnit...	blob \| commitdiff \| raw \| diff to current
2020-07-23	Luke Kenneth Casso...	allow imem to be 64/32 bit wide	blob \| commitdiff \| raw \| diff to current
2020-07-22	Luke Kenneth Casso...	missing ports from issuer, when doing verilog	blob \| commitdiff \| raw \| diff to current
2020-07-22	Luke Kenneth Casso...	reduce number of FastRegs read ports	blob \| commitdiff \| raw \| diff to current
2020-07-21	Luke Kenneth Casso...	add PC (CIA) to PowerDecode2 "state" for passing into...	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	expose core_stop_i to outside as well	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	set go_insn_i to non-resetless	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	update to expose signals at top-level of issuer	blob \| commitdiff \| raw \| diff to current
2020-07-18	Luke Kenneth Casso...	add option to generate verilog	blob \| commitdiff \| raw \| diff to current
2020-07-14	Luke Kenneth Casso...	add MSR reading to issue FSM	blob \| commitdiff \| raw \| diff to current
2020-07-12	Luke Kenneth Casso...	rename InternalOp to MicrOp	blob \| commitdiff \| raw \| diff to current
2020-07-12	Luke Kenneth Casso...	exit FSM when termination detected	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	sort-of got binary execution test working	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	code-shuffle on testing to prepare loading large files...	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	add core start/stop capability, and OP_ATTN support	blob \| commitdiff \| raw \| diff to current
2020-07-06	Luke Kenneth Casso...	add mul unit to test_issuer	blob \| commitdiff \| raw \| diff to current
2020-07-05	Luke Kenneth Casso...	add slow spr regfile regspec support	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	allow flexible selection of the types of ALUs	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	add bare wishbone option to TestIssuer, sort out ports	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	use single-arg pspec for TestIssuer and Core	blob \| commitdiff \| raw \| diff to current
2020-07-01	Luke Kenneth Casso...	add name "test_issuer" to ilang conversion	blob \| commitdiff \| raw \| diff to current
2020-06-28	Luke Kenneth Casso...	read from instruction memory using FetchUnitInterface	blob \| commitdiff \| raw \| diff to current
2020-06-28	Luke Kenneth Casso...	expand instruction bus width to 64 bit, start on a...	blob \| commitdiff \| raw \| diff to current
2020-06-27	Luke Kenneth Casso...	make PortInterface modules consistent with same API	blob \| commitdiff \| raw \| diff to current
2020-06-18	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-06-18	Luke Kenneth Casso...	got loop example operational by noting when PC fastreg...	blob \| commitdiff \| raw \| diff to current
2020-06-18	Luke Kenneth Casso...	slightly hacky way to keep an eye on the PC	blob \| commitdiff \| raw \| diff to current
2020-06-17	Luke Kenneth Casso...	split out TestIssuer into separate module	blob \| commitdiff \| raw \| diff to current

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