Fetch and decode the SVP64 prefix
[soc.git] / src / soc / simple / issuer.py
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex...
2020-10-11 Luke Kenneth Casso... litex sim.py operational
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict...
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-08 Luke Kenneth Casso... create a special subset of Decoder Record for storing...
2020-09-08 Luke Kenneth Casso... pass in state into PowerDecode2, save on eqs and wires
2020-09-07 Luke Kenneth Casso... add per-FU PowerDecoders. should now be subsettable
2020-09-06 Luke Kenneth Casso... copy dec SPR into decoder cur_state
2020-09-06 Luke Kenneth Casso... wark-wark, fast regs is binary-addressed
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer
2020-09-05 Luke Kenneth Casso... add comments on MSR read
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle
2020-09-05 Luke Kenneth Casso... sync on ICP eint
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer
2020-09-04 Luke Kenneth Casso... bring out XICS ICS interrupt levels so that they can...
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Luke Kenneth Casso... bring "core stopped" signal out through DMI interface
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-16 Luke Kenneth Casso... read delay on getting regfile data
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... ha! "state" (pc, msr) not properly passed to core
2020-08-14 Luke Kenneth Casso... drop in insn_state synchronously in issuer, at same...
2020-08-14 Luke Kenneth Casso... finally, fix decoder combinatorial loop
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state,
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-13 Luke Kenneth Casso... fix dmi reg read
2020-08-13 Luke Kenneth Casso... sync on pc writing when changed
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-09 Luke Kenneth Casso... fix combinatorial loop in ldst compunit
2020-08-09 Luke Kenneth Casso... use rising edge detection on st go_i/rel_o
2020-08-09 Luke Kenneth Casso... get rid of MSR read combinatorial loop
2020-08-09 Luke Kenneth Casso... delay go_st by one cycle, break combinatorial loop
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and...
2020-08-04 Luke Kenneth Casso... read/set pc outside of FSM so that DMI interface can...
2020-08-04 Luke Kenneth Casso... whoops must output NIA not PC to debug DMI query in...
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Luke Kenneth Casso... pass state (MSR/PC) around between PowerDecode2, DMI...
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-31 Luke Kenneth Casso... restrict external port list further in test_issuer
2020-07-30 Luke Kenneth Casso... core_start/stop/endian were inverted (output)
2020-07-30 Luke Kenneth Casso... ha! have to explicitly specify the ports when writing...
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide
2020-07-22 Luke Kenneth Casso... missing ports from issuer, when doing verilog
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into...
2020-07-19 Luke Kenneth Casso... expose core_stop_i to outside as well
2020-07-19 Luke Kenneth Casso... set go_insn_i to non-resetless
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer
2020-07-18 Luke Kenneth Casso... add option to generate verilog
2020-07-14 Luke Kenneth Casso... add MSR reading to issue FSM
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... exit FSM when termination detected
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support
2020-07-06 Luke Kenneth Casso... add mul unit to test_issuer
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
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