projects / soc.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Begin to implement the Simple-V loop
[soc.git] / src / soc / simple / issuer.py
2021-03-06 Cesar StraussBegin to implement the Simple-V loop blob | commitdiff | raw
2021-03-06 Cesar StraussDo not reset pc_changed and sv_changed at instruction end blob | commitdiff | raw | diff to current
2021-03-06 Cesar StraussMake the raw opcode input port of the decoder stay... blob | commitdiff | raw | diff to current
2021-03-05 Luke Kenneth Casso... litex expects wishbone "err" signals even if not used blob | commitdiff | raw | diff to current
2021-03-05 Cesar StraussMove writing of the PC state register to the issue FSM blob | commitdiff | raw | diff to current
2021-03-05 Cesar StraussMove the wait on "core stop" out of fetch, and into... blob | commitdiff | raw | diff to current
2021-03-03 Luke Kenneth Casso... cur_state is a global, does not have to be passed as... blob | commitdiff | raw | diff to current
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i blob | commitdiff | raw | diff to current
2021-02-26 Luke Kenneth Casso... remove sv_changed input to fetch_fsm, add it to issue_f... blob | commitdiff | raw | diff to current
2021-02-26 Luke Kenneth Casso... moving new_svstate and update_svstate into issue FSM... blob | commitdiff | raw | diff to current
2021-02-26 Luke Kenneth Casso... move fetch_insn_o into issue_fsm TestIssuer blob | commitdiff | raw | diff to current
2021-02-26 Luke Kenneth Casso... add comments, missing that VL loop ends after execution... blob | commitdiff | raw | diff to current
2021-02-26 Cesar StraussImplement a decode/issue FSM between fetch and execute blob | commitdiff | raw | diff to current
2021-02-23 Luke Kenneth Casso... add note that SVSTATE has changed, this will allow... blob | commitdiff | raw | diff to current
2021-02-22 Luke Kenneth Casso... move setting of NIA into fetch FSM in TestIssuer blob | commitdiff | raw | diff to current
2021-02-22 Luke Kenneth Casso... moving PC-setting (NIA) out of execute_fsm in TestIssuer blob | commitdiff | raw | diff to current
2021-02-22 Luke Kenneth Casso... rename inter-FSM handshake signals in TestIssuer blob | commitdiff | raw | diff to current
2021-02-21 Luke Kenneth Casso... err trying to put in some FSM handshake signals, gettin... blob | commitdiff | raw | diff to current
2021-02-21 Luke Kenneth Casso... comment for where SVSTATE FSM should go blob | commitdiff | raw | diff to current
2021-02-21 Luke Kenneth Casso... move execute_fsm to separate function in TestIssuer blob | commitdiff | raw | diff to current
2021-02-21 Luke Kenneth Casso... move fetch_fsm to separate function in TestIssuer blob | commitdiff | raw | diff to current
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs blob | commitdiff | raw | diff to current
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... blob | commitdiff | raw | diff to current
2021-02-20 Luke Kenneth Casso... whoops spelling error blob | commitdiff | raw | diff to current
2021-02-20 Luke Kenneth Casso... add (unused) code for writing out SVSTATE in TestIssuer blob | commitdiff | raw | diff to current
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... blob | commitdiff | raw | diff to current
2021-02-14 Cesar StraussRemove obsolete comment blob | commitdiff | raw | diff to current
2021-02-14 Luke Kenneth Casso... add comments to TestIssuer blob | commitdiff | raw | diff to current
2021-02-14 Luke Kenneth Casso... add SVSTATE reading to TestIssuer blob | commitdiff | raw | diff to current
2021-02-14 Luke Kenneth Casso... add extra FSM explanatory comments to TestIssuer blob | commitdiff | raw | diff to current
2021-02-13 Luke Kenneth Casso... use function for getting instruction from 32/64 bit... blob | commitdiff | raw | diff to current
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix blob | commitdiff | raw | diff to current
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder blob | commitdiff | raw | diff to current
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM blob | commitdiff | raw | diff to current
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18... blob | commitdiff | raw | diff to current
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180 blob | commitdiff | raw | diff to current
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL blob | commitdiff | raw | diff to current
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB blob | commitdiff | raw | diff to current
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer blob | commitdiff | raw | diff to current
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock blob | commitdiff | raw | diff to current
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere blob | commitdiff | raw | diff to current
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim blob | commitdiff | raw | diff to current
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex... blob | commitdiff | raw | diff to current
2020-10-11 Luke Kenneth Casso... litex sim.py operational blob | commitdiff | raw | diff to current
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly blob | commitdiff | raw | diff to current
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan blob | commitdiff | raw | diff to current
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux... blob | commitdiff | raw | diff to current
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict... blob | commitdiff | raw | diff to current
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180 blob | commitdiff | raw | diff to current
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock... blob | commitdiff | raw | diff to current
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right blob | commitdiff | raw | diff to current
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module blob | commitdiff | raw | diff to current
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog blob | commitdiff | raw | diff to current
2020-09-08 Luke Kenneth Casso... create a special subset of Decoder Record for storing... blob | commitdiff | raw | diff to current
2020-09-08 Luke Kenneth Casso... pass in state into PowerDecode2, save on eqs and wires blob | commitdiff | raw | diff to current
2020-09-07 Luke Kenneth Casso... add per-FU PowerDecoders. should now be subsettable blob | commitdiff | raw | diff to current
2020-09-06 Luke Kenneth Casso... copy dec SPR into decoder cur_state blob | commitdiff | raw | diff to current
2020-09-06 Luke Kenneth Casso... wark-wark, fast regs is binary-addressed blob | commitdiff | raw | diff to current
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB blob | commitdiff | raw | diff to current
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... add comments on MSR read blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... sync on ICP eint blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint blob | commitdiff | raw | diff to current
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer blob | commitdiff | raw | diff to current
2020-09-04 Luke Kenneth Casso... bring out XICS ICS interrupt levels so that they can... blob | commitdiff | raw | diff to current
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts. blob | commitdiff | raw | diff to current
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py blob | commitdiff | raw | diff to current
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface blob | commitdiff | raw | diff to current
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc blob | commitdiff | raw | diff to current
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface blob | commitdiff | raw | diff to current
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc blob | commitdiff | raw | diff to current
2020-08-23 Luke Kenneth Casso... bring "core stopped" signal out through DMI interface blob | commitdiff | raw | diff to current
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus blob | commitdiff | raw | diff to current
2020-08-16 Luke Kenneth Casso... read delay on getting regfile data blob | commitdiff | raw | diff to current
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and... blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... ha! "state" (pc, msr) not properly passed to core blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... drop in insn_state synchronously in issuer, at same... blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... finally, fix decoder combinatorial loop blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state, blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core blob | commitdiff | raw | diff to current
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new... blob | commitdiff | raw | diff to current
2020-08-13 Luke Kenneth Casso... fix dmi reg read blob | commitdiff | raw | diff to current
2020-08-13 Luke Kenneth Casso... sync on pc writing when changed blob | commitdiff | raw | diff to current
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing blob | commitdiff | raw | diff to current
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile blob | commitdiff | raw | diff to current
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports blob | commitdiff | raw | diff to current
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc blob | commitdiff | raw | diff to current
2020-08-09 Luke Kenneth Casso... fix combinatorial loop in ldst compunit blob | commitdiff | raw | diff to current
2020-08-09 Luke Kenneth Casso... use rising edge detection on st go_i/rel_o blob | commitdiff | raw | diff to current
2020-08-09 Luke Kenneth Casso... get rid of MSR read combinatorial loop blob | commitdiff | raw | diff to current
2020-08-09 Luke Kenneth Casso... delay go_st by one cycle, break combinatorial loop blob | commitdiff | raw | diff to current
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc blob | commitdiff | raw | diff to current
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and... blob | commitdiff | raw | diff to current
2020-08-04 Luke Kenneth Casso... read/set pc outside of FSM so that DMI interface can... blob | commitdiff | raw | diff to current
2020-08-04 Luke Kenneth Casso... whoops must output NIA not PC to debug DMI query in... blob | commitdiff | raw | diff to current
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim blob | commitdiff | raw | diff to current
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9 blob | commitdiff | raw | diff to current
2020-08-03 Luke Kenneth Casso... pass state (MSR/PC) around between PowerDecode2, DMI... blob | commitdiff | raw | diff to current
next