Decode and fetch integer predicate registers
[soc.git] / src / soc / simple / issuer.py
2021-03-22 Cesar StraussDecode and fetch integer predicate registers
2021-03-21 Cesar StraussFix typo
2021-03-21 Cesar StraussAdd unique name to decoded predication signals
2021-03-21 Cesar StraussRevert removal of *.value from Enums
2021-03-21 Cesar StraussFix syntax
2021-03-21 Luke Kenneth Casso... more TODO comments
2021-03-21 Luke Kenneth Casso... add for-loop pseudocode for CR predicate mask reading
2021-03-21 Luke Kenneth Casso... code comments in TestIssuer
2021-03-21 Cesar StraussStart work on the predicate fetch FSM
2021-03-20 Luke Kenneth Casso... more pseudocode in TestIssuer
2021-03-20 Luke Kenneth Casso... add harmless code and commented-out pseudocode for...
2021-03-19 Luke Kenneth Casso... more comments for TestIssuer when adding predication
2021-03-19 Luke Kenneth Casso... comments for TestIssuer get_predint and get_predcr
2021-03-19 Luke Kenneth Casso... add more pieces of predication reading puzzle to TestIssuer
2021-03-19 Luke Kenneth Casso... cleanup TestIssuer (comments)
2021-03-19 Luke Kenneth Casso... spelling
2021-03-19 Luke Kenneth Casso... code-shuffle in TestIssuer, split out setting up periph...
2021-03-19 Luke Kenneth Casso... move duplicated code to a function in TestIssuer
2021-03-18 Luke Kenneth Casso... more hint/comments
2021-03-18 Luke Kenneth Casso... update TestIssuer comments
2021-03-18 Luke Kenneth Casso... add comments on most likely place to put predicate...
2021-03-18 Luke Kenneth Casso... comments TestIssuer, add a stub FSM
2021-03-17 Luke Kenneth Casso... add SVP64 dststep incrementing in PowerDecoder2, Testis...
2021-03-14 Cesar StraussActivate the VL==0 loop with any SVP64 prefix whatsoever
2021-03-12 Luke Kenneth Casso... use PowerDecoder2.loop_continue instead of no_out_vec
2021-03-11 Luke Kenneth Casso... add link of RA_OR_ZERO SVP64 detection
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on
2021-03-08 Luke Kenneth Casso... actually make it possible to disable svp64 on commandli...
2021-03-08 Cesar StraussRemove the unused internal insn_done signal
2021-03-08 Cesar StraussFix argument order to match function declaration
2021-03-07 Cesar StraussMerge WAIT_RESET into INSN_FETCH on the Issue FSM
2021-03-07 Luke Kenneth Casso... move DMI stuff to separate function in issuer.py
2021-03-07 Luke Kenneth Casso... update comments in issuer.py
2021-03-07 Cesar StraussImplement the VL==0 loop
2021-03-06 Cesar StraussAllow updating the PC and SVSTATE registers while stopped
2021-03-06 Cesar StraussBegin to implement the Simple-V loop
2021-03-06 Cesar StraussDo not reset pc_changed and sv_changed at instruction end
2021-03-06 Cesar StraussMake the raw opcode input port of the decoder stay...
2021-03-05 Luke Kenneth Casso... litex expects wishbone "err" signals even if not used
2021-03-05 Cesar StraussMove writing of the PC state register to the issue FSM
2021-03-05 Cesar StraussMove the wait on "core stop" out of fetch, and into...
2021-03-03 Luke Kenneth Casso... cur_state is a global, does not have to be passed as...
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i
2021-02-26 Luke Kenneth Casso... remove sv_changed input to fetch_fsm, add it to issue_f...
2021-02-26 Luke Kenneth Casso... moving new_svstate and update_svstate into issue FSM...
2021-02-26 Luke Kenneth Casso... move fetch_insn_o into issue_fsm TestIssuer
2021-02-26 Luke Kenneth Casso... add comments, missing that VL loop ends after execution...
2021-02-26 Cesar StraussImplement a decode/issue FSM between fetch and execute
2021-02-23 Luke Kenneth Casso... add note that SVSTATE has changed, this will allow...
2021-02-22 Luke Kenneth Casso... move setting of NIA into fetch FSM in TestIssuer
2021-02-22 Luke Kenneth Casso... moving PC-setting (NIA) out of execute_fsm in TestIssuer
2021-02-22 Luke Kenneth Casso... rename inter-FSM handshake signals in TestIssuer
2021-02-21 Luke Kenneth Casso... err trying to put in some FSM handshake signals, gettin...
2021-02-21 Luke Kenneth Casso... comment for where SVSTATE FSM should go
2021-02-21 Luke Kenneth Casso... move execute_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth Casso... move fetch_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth Casso... whoops spelling error
2021-02-20 Luke Kenneth Casso... add (unused) code for writing out SVSTATE in TestIssuer
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussRemove obsolete comment
2021-02-14 Luke Kenneth Casso... add comments to TestIssuer
2021-02-14 Luke Kenneth Casso... add SVSTATE reading to TestIssuer
2021-02-14 Luke Kenneth Casso... add extra FSM explanatory comments to TestIssuer
2021-02-13 Luke Kenneth Casso... use function for getting instruction from 32/64 bit...
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex...
2020-10-11 Luke Kenneth Casso... litex sim.py operational
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict...
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-08 Luke Kenneth Casso... create a special subset of Decoder Record for storing...
2020-09-08 Luke Kenneth Casso... pass in state into PowerDecode2, save on eqs and wires
2020-09-07 Luke Kenneth Casso... add per-FU PowerDecoders. should now be subsettable
2020-09-06 Luke Kenneth Casso... copy dec SPR into decoder cur_state
2020-09-06 Luke Kenneth Casso... wark-wark, fast regs is binary-addressed
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer
2020-09-05 Luke Kenneth Casso... add comments on MSR read
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle
2020-09-05 Luke Kenneth Casso... sync on ICP eint
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint
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