2021-03-22 |
Cesar Strauss | Decode and fetch integer predicate registers |
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2021-03-21 |
Cesar Strauss | Fix typo |
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2021-03-21 |
Cesar Strauss | Add unique name to decoded predication signals |
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2021-03-21 |
Cesar Strauss | Revert removal of *.value from Enums |
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2021-03-21 |
Cesar Strauss | Fix syntax |
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2021-03-21 |
Luke Kenneth Casso... | more TODO comments |
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2021-03-21 |
Luke Kenneth Casso... | add for-loop pseudocode for CR predicate mask reading |
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2021-03-21 |
Luke Kenneth Casso... | code comments in TestIssuer |
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2021-03-21 |
Cesar Strauss | Start work on the predicate fetch FSM |
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2021-03-20 |
Luke Kenneth Casso... | more pseudocode in TestIssuer |
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2021-03-20 |
Luke Kenneth Casso... | add harmless code and commented-out pseudocode for... |
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2021-03-19 |
Luke Kenneth Casso... | more comments for TestIssuer when adding predication |
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2021-03-19 |
Luke Kenneth Casso... | comments for TestIssuer get_predint and get_predcr |
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2021-03-19 |
Luke Kenneth Casso... | add more pieces of predication reading puzzle to TestIssuer |
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2021-03-19 |
Luke Kenneth Casso... | cleanup TestIssuer (comments) |
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2021-03-19 |
Luke Kenneth Casso... | spelling |
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2021-03-19 |
Luke Kenneth Casso... | code-shuffle in TestIssuer, split out setting up periph... |
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2021-03-19 |
Luke Kenneth Casso... | move duplicated code to a function in TestIssuer |
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2021-03-18 |
Luke Kenneth Casso... | more hint/comments |
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2021-03-18 |
Luke Kenneth Casso... | update TestIssuer comments |
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2021-03-18 |
Luke Kenneth Casso... | add comments on most likely place to put predicate... |
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2021-03-18 |
Luke Kenneth Casso... | comments TestIssuer, add a stub FSM |
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2021-03-17 |
Luke Kenneth Casso... | add SVP64 dststep incrementing in PowerDecoder2, Testis... |
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2021-03-14 |
Cesar Strauss | Activate the VL==0 loop with any SVP64 prefix whatsoever |
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2021-03-12 |
Luke Kenneth Casso... | use PowerDecoder2.loop_continue instead of no_out_vec |
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2021-03-11 |
Luke Kenneth Casso... | add link of RA_OR_ZERO SVP64 detection |
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2021-03-09 |
Cesar Strauss | Create a new signal for the Simulator to wait on |
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2021-03-08 |
Luke Kenneth Casso... | actually make it possible to disable svp64 on commandli... |
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2021-03-08 |
Cesar Strauss | Remove the unused internal insn_done signal |
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2021-03-08 |
Cesar Strauss | Fix argument order to match function declaration |
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2021-03-07 |
Cesar Strauss | Merge WAIT_RESET into INSN_FETCH on the Issue FSM |
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2021-03-07 |
Luke Kenneth Casso... | move DMI stuff to separate function in issuer.py |
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2021-03-07 |
Luke Kenneth Casso... | update comments in issuer.py |
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2021-03-07 |
Cesar Strauss | Implement the VL==0 loop |
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2021-03-06 |
Cesar Strauss | Allow updating the PC and SVSTATE registers while stopped |
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2021-03-06 |
Cesar Strauss | Begin to implement the Simple-V loop |
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2021-03-06 |
Cesar Strauss | Do not reset pc_changed and sv_changed at instruction end |
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2021-03-06 |
Cesar Strauss | Make the raw opcode input port of the decoder stay... |
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2021-03-05 |
Luke Kenneth Casso... | litex expects wishbone "err" signals even if not used |
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2021-03-05 |
Cesar Strauss | Move writing of the PC state register to the issue FSM |
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2021-03-05 |
Cesar Strauss | Move the wait on "core stop" out of fetch, and into... |
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2021-03-03 |
Luke Kenneth Casso... | cur_state is a global, does not have to be passed as... |
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2021-03-03 |
Luke Kenneth Casso... | add svstate_i to TestIssuer which mirrors pc_i |
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2021-02-26 |
Luke Kenneth Casso... | remove sv_changed input to fetch_fsm, add it to issue_f... |
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2021-02-26 |
Luke Kenneth Casso... | moving new_svstate and update_svstate into issue FSM... |
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2021-02-26 |
Luke Kenneth Casso... | move fetch_insn_o into issue_fsm TestIssuer |
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2021-02-26 |
Luke Kenneth Casso... | add comments, missing that VL loop ends after execution... |
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2021-02-26 |
Cesar Strauss | Implement a decode/issue FSM between fetch and execute |
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2021-02-23 |
Luke Kenneth Casso... | add note that SVSTATE has changed, this will allow... |
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2021-02-22 |
Luke Kenneth Casso... | move setting of NIA into fetch FSM in TestIssuer |
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2021-02-22 |
Luke Kenneth Casso... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
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2021-02-22 |
Luke Kenneth Casso... | rename inter-FSM handshake signals in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | err trying to put in some FSM handshake signals, gettin... |
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2021-02-21 |
Luke Kenneth Casso... | comment for where SVSTATE FSM should go |
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2021-02-21 |
Luke Kenneth Casso... | move execute_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | move fetch_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | add JTAG enable/disable of 4k SRAMs |
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2021-02-20 |
Luke Kenneth Casso... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... |
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2021-02-20 |
Luke Kenneth Casso... | whoops spelling error |
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2021-02-20 |
Luke Kenneth Casso... | add (unused) code for writing out SVSTATE in TestIssuer |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-14 |
Cesar Strauss | Remove obsolete comment |
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2021-02-14 |
Luke Kenneth Casso... | add comments to TestIssuer |
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2021-02-14 |
Luke Kenneth Casso... | add SVSTATE reading to TestIssuer |
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2021-02-14 |
Luke Kenneth Casso... | add extra FSM explanatory comments to TestIssuer |
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2021-02-13 |
Luke Kenneth Casso... | use function for getting instruction from 32/64 bit... |
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2021-02-13 |
Cesar Strauss | Fetch and decode the SVP64 prefix |
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2021-02-11 |
Luke Kenneth Casso... | comments in TestIssuer for SVP64PrefixDecoder |
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2021-02-06 |
Cesar Strauss | Extract the fetch FSM out from the main FSM |
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2020-11-13 |
Luke Kenneth Casso... | reduce clkcsel ls180 width (2 pins), rename pll_18... |
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2020-11-13 |
Luke Kenneth Casso... | rename and add pll lock signal to ls180 |
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2020-11-10 |
Luke Kenneth Casso... | remove ClockSelect module, use DummyPLL |
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2020-10-22 |
Luke Kenneth Casso... | add query about cross-domain on the JTAG enable of WB |
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2020-10-22 |
Luke Kenneth Casso... | add JTAG enable/disable of wishbone to TestIssuer |
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2020-10-15 |
Luke Kenneth Casso... | wrong pspec variable in selecting pll clock |
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2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
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2020-10-11 |
Luke Kenneth Casso... | add way to bypass PLL for ECP5 and sim |
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2020-10-11 |
Luke Kenneth Casso... | comment out XICS/GPIO interrupt test, causes ECP5 litex... |
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2020-10-11 |
Luke Kenneth Casso... | litex sim.py operational |
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2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
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2020-10-06 |
Luke Kenneth Casso... | add sdr bypass routing via JTAG boundary scan |
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2020-10-04 |
Luke Kenneth Casso... | significant reorg of the litex pinspecs to use pinmux... |
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2020-10-03 |
Luke Kenneth Casso... | minor reorg on JTAG, allow alternative pinset dict... |
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2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
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2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
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2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
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2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
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2020-09-22 |
Luke Kenneth Casso... | add jtag interface to issuer_verilog |
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2020-09-08 |
Luke Kenneth Casso... | create a special subset of Decoder Record for storing... |
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2020-09-08 |
Luke Kenneth Casso... | pass in state into PowerDecode2, save on eqs and wires |
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2020-09-07 |
Luke Kenneth Casso... | add per-FU PowerDecoders. should now be subsettable |
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2020-09-06 |
Luke Kenneth Casso... | copy dec SPR into decoder cur_state |
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2020-09-06 |
Luke Kenneth Casso... | wark-wark, fast regs is binary-addressed |
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2020-09-06 |
Luke Kenneth Casso... | add comments for DEC / TB |
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2020-09-06 |
Luke Kenneth Casso... | add a DEC/TB FSM to TestIssuer |
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2020-09-05 |
Luke Kenneth Casso... | add comments on MSR read |
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2020-09-05 |
Luke Kenneth Casso... | move GPIO IRQ to 15 to match microwatt modifications |
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2020-09-05 |
Luke Kenneth Casso... | MSR read in INSN_READ only occurs for 1 cycle |
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2020-09-05 |
Luke Kenneth Casso... | sync on ICP eint |
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2020-09-05 |
Luke Kenneth Casso... | connect XICS core irq to Decode2 eint |
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