rename InternalOp to MicrOp
[soc.git] / src / soc / simple / issuer.py
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... exit FSM when termination detected
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support
2020-07-06 Luke Kenneth Casso... add mul unit to test_issuer
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... got loop example operational by noting when PC fastreg...
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module