use "enable" and set default actions in getopt
[soc.git] / src / soc / simple / issuer_verilog.py
2020-10-15 Luke Kenneth Casso... use "enable" and set default actions in getopt
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using...
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim
2020-10-11 Luke Kenneth Casso... litex sim.py operational
2020-09-28 Luke Kenneth Casso... add "nocore" option to build verilog
2020-09-28 Luke Kenneth Casso... switch off internal gpio (testing)
2020-09-22 Luke Kenneth Casso... add jtagremote to litex sim, add new "variant" to core...
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-19 Luke Kenneth Casso... remove the gpio peripheral which was previously hard...
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Luke Kenneth Casso... testing 64-bit wishbone bus after 32-bit *still* fails...
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-14 Luke Kenneth Casso... put multi-ports back (for read) on int and fast regfiles
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and...
2020-07-30 Luke Kenneth Casso... ha! have to explicitly specify the ports when writing...
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-19 Luke Kenneth Casso... add issuer verilog generator