raise interrupt on misaligned atomic LDST
[soc.git] / src / soc / simple / test / test_core.py
2021-12-25 Luke Kenneth Casso... wait for MMU "done" when setting PRTBL and PIDR
2021-12-20 Luke Kenneth Casso... set up DAR correctly in unit tests, added set_ldst_spr...
2021-12-16 Luke Kenneth Casso... set_mmu_spr was using the slow-SPR index for the regfile
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth Casso... FunctionUnitBaseMulti which derives from ReservationSta...
2021-11-30 Luke Kenneth Casso... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth Casso... add LogicalTestCases back in to test_core.py (pass)
2021-11-30 Luke Kenneth Casso... let PowerDecode2 decide which operand class to use...
2021-11-30 Luke Kenneth Casso... allow busy to settle before checking state in test_core.py
2021-11-30 Luke Kenneth Casso... only check regs right at the end in test_core.py overla...
2021-11-30 Luke Kenneth Casso... move sim call before core run in test_core.py
2021-11-30 Luke Kenneth Casso... getting formerly unused test_core.py operational
2021-11-10 Luke Kenneth Casso... allow MSR to be set in StateRegs in test_core.py
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-22 Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
2021-09-22 Luke Kenneth Casso... whoops forgot to do with self.subTest()
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 klehmanchanged over to use state mem compare
2021-09-16 Luke Kenneth Casso... moving teststate_check_regs written by klehman into...
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-14 Luke Kenneth Casso... convert to using TestState and State after moving to...
2021-09-12 Luke Kenneth Casso... code comments
2021-09-12 Luke Kenneth Casso... create new function teststate_check_regs which is calle...
2021-09-12 klehmanchanges to utilize full teststate class
2021-09-10 klehmanchanges made to utilize teststate class
2021-09-07 Luke Kenneth Casso... fun fixing of get_core_hdl_regs, "yield from"
2021-09-07 Luke Kenneth Casso... move functions to above where they are called
2021-09-07 klehmanbreakout of register collection and compare
2021-09-07 Cesar StraussFix typo.
2021-09-07 Luke Kenneth Casso... add TODO code-comments
2021-09-07 Luke Kenneth Casso... whitespace, add bug ref number to test API
2021-08-29 Luke Kenneth Casso... unnecessary signal rename ivalid_i to ii_valid (reverting)
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-05-01 Luke Kenneth Casso... use new AllFunctionUnits.get_fu function
2021-05-01 Luke Kenneth Casso... use SPRreduced to match PowerDecoder2
2021-04-30 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=635
2021-04-30 Luke Kenneth Casso... better reporting on gpr comparisons
2021-04-23 Luke Kenneth Casso... error in setting fast regs test values
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction
2021-01-18 Tobias Platenuncomment #FIXME in unit_test
2021-01-08 Tobias Platenfix broken testcase for simple core
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-11 Luke Kenneth Casso... fix spr setting, set endianness
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... sorting out setting of XER
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN)
2020-07-07 Luke Kenneth Casso... debugging termination / OP_ATTN
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth Casso... move debug statements to check function
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests...
2020-06-08 Luke Kenneth Casso... re-add unit tests back in
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... code-morph test_core for XER bit clarity
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not...
2020-06-07 Luke Kenneth Casso... assert XER SO/OV/CA registers, check these are ok ...
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in...
2020-06-07 Luke Kenneth Casso... add msr to ISA in test_core.py
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right
2020-06-04 Luke Kenneth Casso... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth Casso... remove unneeded code
2020-06-04 Luke Kenneth Casso... add branch test case to core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... add ShiftRot test case (works only because CRs are...
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