set defaults in pspec
[soc.git] / src / soc / simple / test / test_issuer.py
2020-10-16 Luke Kenneth Casso... set defaults in pspec
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-08 Luke Kenneth Casso... add cxxsim option
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working)
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state,
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-09 Luke Kenneth Casso... add logical test issuer case
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div test cases into test_issuer.py
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... activate some of new accumulator-based tests in test_issuer
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for...
2020-07-12 Luke Kenneth Casso... add OP_ATTN test back in
2020-07-12 Luke Kenneth Casso... msb of instruction causing sign-overflow
2020-07-11 Luke Kenneth Casso... more setting bigendian
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... got test_issuer operational on one unit test
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN)
2020-07-07 Luke Kenneth Casso... update opcode map for OP_ATTN
2020-07-07 Luke Kenneth Casso... debugging termination / OP_ATTN
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py
2020-07-05 Luke Kenneth Casso... add SPR test case, commented out for now
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer