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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
simple
/
test
/ test_issuer_mmu.py
2021-12-04
Luke Kenneth Casso...
whoops
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2021-12-04
Luke Kenneth Casso...
MMU lookup DSISR load bit inverted in LoadStore1
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2021-12-03
Luke Kenneth Casso...
add misaligned ld/st to trigger an exception
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2021-11-10
Luke Kenneth Casso...
update store data reg 10 to 0xfe in virtmode mmu test
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2021-11-10
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-11-10
Tobias Platen
test testcase for exception
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2021-11-09
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-11-09
Tobias Platen
test_issuer_mmu.py: add case_5_allsprs
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2021-11-08
Tobias Platen
mmu unit test working again
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2021-11-06
Tobias Platen
update test_issuer_mmu.py testcase, add needed debug...
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2021-11-05
Tobias Platen
tlbie, mtspr and mfspr test cases
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2021-11-05
Tobias Platen
add mmu/dcache unit test
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2021-09-25
Las Safin
Merge remote-tracking branch 'upstream/master' into pr
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2021-09-08
Cesar Strauss
Monitor exceptions, re-decoding the instruction in...
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2021-08-17
Cesar Strauss
Enable LD/ST exception test case
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2021-05-12
Luke Kenneth Casso...
bit of a hack to get test_mmu_dcache_pi.py operational.
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2021-05-10
Luke Kenneth Casso...
add block for MMU activation to LoadStore1
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2021-05-09
Luke Kenneth Casso...
add comments in LoadStore1
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2021-05-09
Luke Kenneth Casso...
run LD/ST Exception test case for MMU
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2021-05-01
Luke Kenneth Casso...
store data in microwatt dcache goes in one cycle AFTER...
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2021-05-01
Luke Kenneth Casso...
add LD/ST cases to MMU, which should all still work
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2021-05-01
Luke Kenneth Casso...
add MMUTestCaseROM
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2021-04-30
Luke Kenneth Casso...
add basic test_issuer_mmu.py
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