sort out misaligned store in LoadStore1
[soc.git] / src / soc / simple / test / test_issuer_mmu.py
2021-12-04 Luke Kenneth Casso... whoops
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-03 Luke Kenneth Casso... add misaligned ld/st to trigger an exception
2021-11-10 Luke Kenneth Casso... update store data reg 10 to 0xfe in virtmode mmu test
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Tobias Platentest testcase for exception
2021-11-09 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-09 Tobias Platentest_issuer_mmu.py: add case_5_allsprs
2021-11-08 Tobias Platenmmu unit test working again
2021-11-06 Tobias Platenupdate test_issuer_mmu.py testcase, add needed debug...
2021-11-05 Tobias Platentlbie, mtspr and mfspr test cases
2021-11-05 Tobias Platenadd mmu/dcache unit test
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-08-17 Cesar StraussEnable LD/ST exception test case
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational.
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth Casso... add LD/ST cases to MMU, which should all still work
2021-05-01 Luke Kenneth Casso... add MMUTestCaseROM
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py