sort out misaligned store in LoadStore1
[soc.git] / src / soc / simple / test / teststate.py
2021-12-18 Luke Kenneth Casso... add icache/dcache/mmu unit test for TestIssuer
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth Casso... getting formerly unused test_core.py operational
2021-11-11 Luke Kenneth Casso... invert numbering on CR HDLState.get_crregs
2021-10-08 klehmanadded comment to teststate
2021-10-07 klehmanadded comment to teststate
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Luke Kenneth Casso... convert HDLState.get_mem() to a dictionary of memory...
2021-09-20 Luke Kenneth Casso... use get_l0_mem in HDLState to get memory data
2021-09-18 Luke Kenneth Casso... always store full memory state (including zeros)
2021-09-18 klehmanadded get_mem
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-14 Luke Kenneth Casso... convert to using TestState and State after moving to...
2021-09-14 klehmanfactory add and intro doc string
2021-09-12 Luke Kenneth Casso... use log instead of print
2021-09-12 Luke Kenneth Casso... create new function teststate_check_regs which is calle...
2021-09-12 klehmanadded compare function
2021-09-12 klehmanadded factory function for test class creation
2021-09-10 klehmanimplement base class in state class
2021-09-09 klehmanmade sim into generators and some uniformity changes
2021-09-09 klehmanfinished remaining hdl items
2021-09-09 klehmanHDL int reg added
2021-09-09 klehmanmore sim class registers add
2021-09-08 klehmaninitial commit of sim state class