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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
simple
/
test
/
teststate.py
2022-08-14
Luke Kenneth Casso...
grr not a yield function
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2022-08-14
Luke Kenneth Casso...
add get_fpregs stub function to HDLstate
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2021-12-18
Luke Kenneth Casso...
add icache/dcache/mmu unit test for TestIssuer
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2021-11-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-11-30
Luke Kenneth Casso...
getting formerly unused test_core.py operational
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2021-11-11
Luke Kenneth Casso...
invert numbering on CR HDLState.get_crregs
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2021-10-08
klehman
added comment to teststate
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2021-10-07
klehman
added comment to teststate
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2021-09-25
Las Safin
Merge remote-tracking branch 'upstream/master' into pr
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2021-09-21
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-09-21
Luke Kenneth Casso...
convert HDLState.get_mem() to a dictionary of memory...
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2021-09-20
Luke Kenneth Casso...
use get_l0_mem in HDLState to get memory data
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2021-09-18
Luke Kenneth Casso...
always store full memory state (including zeros)
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2021-09-18
klehman
added get_mem
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2021-09-15
isengaara
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-09-14
Luke Kenneth Casso...
convert to using TestState and State after moving to...
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2021-09-14
klehman
factory add and intro doc string
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2021-09-12
Luke Kenneth Casso...
use log instead of print
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2021-09-12
Luke Kenneth Casso...
create new function teststate_check_regs which is calle...
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2021-09-12
klehman
added compare function
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2021-09-12
klehman
added factory function for test class creation
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2021-09-10
klehman
implement base class in state class
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2021-09-09
klehman
made sim into generators and some uniformity changes
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2021-09-09
klehman
finished remaining hdl items
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2021-09-09
klehman
HDL int reg added
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2021-09-09
klehman
more sim class registers add
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2021-09-08
klehman
initial commit of sim state class
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