radix: reading first page table entry
[soc.git] / src / soc / simple / test /
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on
2021-03-08 Luke Kenneth Casso... actually make it possible to disable svp64 on commandli...
2021-03-08 Luke Kenneth Casso... add option in TestRunner to disable svp64 via commandli...
2021-03-03 Luke Kenneth Casso... set SVSTATE in TestRunner using new TestIssuer.svstate_i
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2021-02-27 Cesar StraussAdd traces for the new FSM
2021-02-24 Tobias Platentest_runner.py: add needed imports
2021-02-23 Tobias Platendeduplicate
2021-02-22 Luke Kenneth Casso... whoops
2021-02-22 Luke Kenneth Casso... moving PC-setting (NIA) out of execute_fsm in TestIssuer
2021-02-21 Cesar StraussHide the register augmentation traces by default
2021-02-21 Luke Kenneth Casso... move fetch_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2021-02-20 Luke Kenneth Casso... whoops set ROM to none by mistake
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging...
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding...
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the...
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussShow traces for the register numbers of the current...
2021-02-14 Luke Kenneth Casso... add TestRunner comments
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test
2021-02-13 Luke Kenneth Casso... split out TestRunner into separate module
2021-02-12 Luke Kenneth Casso... add SVSTATE to TestCase infrastructure for use in TestI...
2021-02-06 Cesar StraussFix whitespace
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when...
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer
2021-01-18 Tobias Platenuncomment #FIXME in unit_test
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-08 Tobias Platenfix broken testcase for simple core
2020-10-16 Luke Kenneth Casso... re-enable tests
2020-10-16 Luke Kenneth Casso... manually run coresync clock for test issuer
2020-10-16 Luke Kenneth Casso... set defaults in pspec
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-08 Luke Kenneth Casso... add cxxsim option
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working)
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state,
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-09 Luke Kenneth Casso... add logical test issuer case
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div test cases into test_issuer.py
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... activate some of new accumulator-based tests in test_issuer
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for...
2020-07-12 Luke Kenneth Casso... add OP_ATTN test back in
2020-07-12 Luke Kenneth Casso... msb of instruction causing sign-overflow
2020-07-11 Luke Kenneth Casso... fix spr setting, set endianness
2020-07-11 Luke Kenneth Casso... more setting bigendian
2020-07-11 Luke Kenneth Casso... add bigendian mode to helloworld test
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... sorting out setting of XER
2020-07-08 Luke Kenneth Casso... got test_issuer operational on one unit test
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking...
2020-07-08 Luke Kenneth Casso... copy binary loaded from disk into data memory as well
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add hello world binary test
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN)
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