disallow overlap in core on LDST, Branch, and Trap.
[soc.git] / src / soc / simple /
2 hours ago Luke Kenneth Casso... disallow overlap in core on LDST, Branch, and Trap. master
2 hours ago Luke Kenneth Casso... use dict style not setattr on submodules
46 hours ago Luke Kenneth Casso... code-comments
46 hours ago Luke Kenneth Casso... fix instructions of the type "read-reg-is-same-as-write"
4 days ago Luke Kenneth Casso... convert hazard bitvectors to Reset-Priority SRLatch...
4 days ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
4 days ago Luke Kenneth Casso... fix write-after-write hazard detection
4 days ago Luke Kenneth Casso... when allow_overlap enabled do a manual wait until all...
4 days ago Luke Kenneth Casso... code-comments
4 days ago Luke Kenneth Casso... add write-after-write hazard detection
5 days ago Luke Kenneth Casso... whoops merged the two write-ports for RT and RA-with...
5 days ago Luke Kenneth Casso... disable hazard vectors when overlap is not requested...
5 days ago Luke Kenneth Casso... more comments
5 days ago Luke Kenneth Casso... add FU write-after-write hazard detection Signal (dummy...
5 days ago Luke Kenneth Casso... add code-comments, link to in-order core
5 days ago Luke Kenneth Casso... more use of namedtuples in core.py for clarity
6 days ago Luke Kenneth Casso... start some use of namedtuples in core.py
6 days ago Luke Kenneth Casso... use some namedtuples to make things clearer in core.py
6 days ago Luke Kenneth Casso... use fascinating trick of defaultdict-of-defaultdicts
6 days ago Luke Kenneth Casso... make FetchFSM take PC as an input in its ispec
6 days ago Luke Kenneth Casso... local variable rename in FetchFSM
6 days ago Luke Kenneth Casso... split out FetchFSM into separate module
7 days ago Luke Kenneth Casso... whoops accidentally committed commented-out test for...
7 days ago Luke Kenneth Casso... reset execute back to ISSUE_START if at INSN_WAIT and
7 days ago Luke Kenneth Casso... restrict (refine) hazard selection to the one being...
7 days ago Luke Kenneth Casso... block picker hazard on input to PriorityPicker rather...
7 days ago Luke Kenneth Casso... parse test_issuer args allow option "allow-overlap...
7 days ago Luke Kenneth Casso... complex. TestRunner now does not work properly unless...
7 days ago Luke Kenneth Casso... fixed issue with hazard dependencies, read will nott
9 days ago Luke Kenneth Casso... add both bitdict and selected args to connect_rd/wrport
9 days ago Luke Kenneth Casso... sorting out issue hazard conflicts in core.
9 days ago Luke Kenneth Casso... debug and cleanup
9 days ago Luke Kenneth Casso... rename instruction_active to instr_active in core
9 days ago Luke Kenneth Casso... read latch on regfile ports was fine, the combinatorial...
9 days ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
9 days ago Luke Kenneth Casso... latch copy of read register numbers, not in use due...
9 days ago Luke Kenneth Casso... use read spec in connect_rdport rather than list of...
9 days ago Luke Kenneth Casso... capture write regfile numbers into write latches in...
9 days ago Luke Kenneth Casso... code tidyup / comments, and use defaultdict
9 days ago Luke Kenneth Casso... create lists of latches in each FU, to record the read...
10 days ago Luke Kenneth Casso... remove combinatorial loop in core instruction conflict...
10 days ago Luke Kenneth Casso... experimenting with overlapping instructions, bit of...
10 days ago Luke Kenneth Casso... set up core processing FSM, which captures data if...
10 days ago Luke Kenneth Casso... set up a temporary copy of CoreInput
10 days ago Luke Kenneth Casso... experiment allowing overlap (activated with --allow...
10 days ago Luke Kenneth Casso... remove unneeded import
11 days ago Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
11 days ago Luke Kenneth Casso... reading of regfile bitvector added, which activates...
11 days ago Luke Kenneth Casso... add option to test_issuer.py to allow for overlapping...
11 days ago Luke Kenneth Casso... add ability to run hazard instruction for test purposes
11 days ago Luke Kenneth Casso... detect the case in Core bitvector when the Function...
11 days ago Luke Kenneth Casso... missing optional check on make_hazard_vecs
11 days ago Luke Kenneth Casso... move core hazard set/clear to separate function, for...
11 days ago Luke Kenneth Casso... whoops context-indentation by mistake (no harm done...
11 days ago Luke Kenneth Casso... add a FetchOutput pipeline data structure
12 days ago Luke Kenneth Casso... print out regfile unary status, bit of name-cleanup
12 days ago Luke Kenneth Casso... use a virtual regfile port for the hazard bitvectors
12 days ago Luke Kenneth Casso... create set/get ports for bitvectors
12 days ago Luke Kenneth Casso... capture write port (wrflag) in byregfiles_spec for...
12 days ago Luke Kenneth Casso... rename regports for bitvectors so that
13 days ago Luke Kenneth Casso... starting to get write-clear of hazard vectors operating
2021-11-13 Luke Kenneth Casso... start adding hazard vector setting in core (unfinished)
2021-11-11 Luke Kenneth Casso... debug prints
2021-11-11 Luke Kenneth Casso... fix regfile port names for "fast" port access (regreduc...
2021-11-11 Luke Kenneth Casso... code-comments
2021-11-11 Luke Kenneth Casso... split out core input/output into separate file core_data.py
2021-11-11 Luke Kenneth Casso... enable hazard vecs in core
2021-11-11 Luke Kenneth Casso... invert numbering on CR HDLState.get_crregs
2021-11-10 Luke Kenneth Casso... update store data reg 10 to 0xfe in virtmode mmu test
2021-11-10 Luke Kenneth Casso... allow MSR to be set in StateRegs in test_core.py
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Tobias Platentest testcase for exception
2021-11-10 Luke Kenneth Casso... make core busy_o part of the CoreOutput data structure
2021-11-10 Luke Kenneth Casso... add a "fu_found" signal to core, which allows for an...
2021-11-09 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-09 Tobias Platentest_issuer_mmu.py: add case_5_allsprs
2021-11-09 Luke Kenneth Casso... add core instruction-issue PriorityPickers
2021-11-09 Luke Kenneth Casso... comments
2021-11-09 Luke Kenneth Casso... core.py: create a dictionary of lists of Function Units...
2021-11-09 Luke Kenneth Casso... create function core conect_satellite_decoders
2021-11-08 Luke Kenneth Casso... shorter way of getting FU busy signals
2021-11-08 Luke Kenneth Casso... MultiCompUnit fixed to not need rdmask to be sustained...
2021-11-08 Tobias Platenmmu unit test working again
2021-11-08 Luke Kenneth Casso... remove unused variable
2021-11-08 Luke Kenneth Casso... code comments
2021-11-08 Luke Kenneth Casso... comments
2021-11-08 Luke Kenneth Casso... remove issue_i from core, use i_valid instead to decide...
2021-11-08 Luke Kenneth Casso... move "exception happened" detection from TestIssuer...
2021-11-08 Luke Kenneth Casso... use p.i_valid in core instead of explicit signal ivalid_i
2021-11-08 Luke Kenneth Casso... use Pipeline API o_ready instead of explicit core busy_...
2021-11-08 Luke Kenneth Casso... convert core.py to Pipeline API, deriving from ControlBase
2021-11-08 Luke Kenneth Casso... move simple core input and output data to in/out data...
2021-11-07 Luke Kenneth Casso... for some reason mul test cases had not been added to...
2021-11-06 Tobias Platenupdate test_issuer_mmu.py testcase, add needed debug...
2021-11-05 Tobias Platentlbie, mtspr and mfspr test cases
2021-11-05 Tobias Platenadd mmu/dcache unit test
2021-11-04 Luke Kenneth Casso... add name to write pick on core
2021-11-01 Tobias Platentest_issuer_dcache.py: cleanup
2021-11-01 Luke Kenneth Casso... code comments for core
2021-10-08 klehmancomments for test_runner pr
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