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remove ClockSelect module, use DummyPLL
[soc.git] / src / soc / simple /
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL tree | commitdiff
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB tree | commitdiff
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer tree | commitdiff
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f... tree | commitdiff
2020-10-16 Luke Kenneth Casso... re-enable tests tree | commitdiff
2020-10-16 Luke Kenneth Casso... manually run coresync clock for test issuer tree | commitdiff
2020-10-16 Luke Kenneth Casso... set defaults in pspec tree | commitdiff
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock tree | commitdiff
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere tree | commitdiff
2020-10-15 Luke Kenneth Casso... use "enable" and set default actions in getopt tree | commitdiff
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using... tree | commitdiff
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim tree | commitdiff
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex... tree | commitdiff
2020-10-11 Luke Kenneth Casso... litex sim.py operational tree | commitdiff
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly tree | commitdiff
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset tree | commitdiff
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan tree | commitdiff
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux... tree | commitdiff
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict... tree | commitdiff
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180 tree | commitdiff
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock... tree | commitdiff
2020-09-28 Luke Kenneth Casso... missing pspec tree | commitdiff
2020-09-28 Luke Kenneth Casso... add "nocore" option to build verilog tree | commitdiff
2020-09-28 Luke Kenneth Casso... switch off internal gpio (testing) tree | commitdiff
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right tree | commitdiff
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim tree | commitdiff
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among... tree | commitdiff
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module tree | commitdiff
2020-09-22 Luke Kenneth Casso... add jtagremote to litex sim, add new "variant" to core... tree | commitdiff
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog tree | commitdiff
2020-09-22 Luke Kenneth Casso... add MMU (commented out) tree | commitdiff
2020-09-19 Luke Kenneth Casso... remove the gpio peripheral which was previously hard... tree | commitdiff
2020-09-08 Luke Kenneth Casso... create a special subset of Decoder Record for storing... tree | commitdiff
2020-09-08 Luke Kenneth Casso... pass in state into PowerDecode2, save on eqs and wires tree | commitdiff
2020-09-08 Luke Kenneth Casso... give Decode2Execute1Type in core a name tree | commitdiff
2020-09-08 Luke Kenneth Casso... pass in CoreState to PowerDecoder rather than eq a... tree | commitdiff
2020-09-08 Luke Kenneth Casso... add cxxsim option tree | commitdiff
2020-09-07 Luke Kenneth Casso... use PowerDecoderSubsets for FUs, except for TRAP which... tree | commitdiff
2020-09-07 Luke Kenneth Casso... add per-FU PowerDecoders. should now be subsettable tree | commitdiff
2020-09-06 Luke Kenneth Casso... copy dec SPR into decoder cur_state tree | commitdiff
2020-09-06 Luke Kenneth Casso... wark-wark, fast regs is binary-addressed tree | commitdiff
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB tree | commitdiff
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer tree | commitdiff
2020-09-05 Luke Kenneth Casso... add comments on MSR read tree | commitdiff
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications tree | commitdiff
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle tree | commitdiff
2020-09-05 Luke Kenneth Casso... sync on ICP eint tree | commitdiff
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer tree | commitdiff
2020-09-04 Luke Kenneth Casso... bring out XICS ICS interrupt levels so that they can... tree | commitdiff
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts. tree | commitdiff
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR... tree | commitdiff
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py tree | commitdiff
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface tree | commitdiff
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface tree | commitdiff
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working) tree | commitdiff
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-23 Luke Kenneth Casso... bring "core stopped" signal out through DMI interface tree | commitdiff
2020-08-21 Luke Kenneth Casso... testing 64-bit wishbone bus after 32-bit *still* fails... tree | commitdiff
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus tree | commitdiff
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest tree | commitdiff
2020-08-16 Luke Kenneth Casso... read delay on getting regfile data tree | commitdiff
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and... tree | commitdiff
2020-08-14 Luke Kenneth Casso... ha! "state" (pc, msr) not properly passed to core tree | commitdiff
2020-08-14 Luke Kenneth Casso... drop in insn_state synchronously in issuer, at same... tree | commitdiff
2020-08-14 Luke Kenneth Casso... finally, fix decoder combinatorial loop tree | commitdiff
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state, tree | commitdiff
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core tree | commitdiff
2020-08-14 Luke Kenneth Casso... move regspec / rdflag decoding functions out of PowerDe... tree | commitdiff
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new... tree | commitdiff
2020-08-14 Luke Kenneth Casso... put multi-ports back (for read) on int and fast regfiles tree | commitdiff
2020-08-13 Luke Kenneth Casso... fix dmi reg read tree | commitdiff
2020-08-13 Luke Kenneth Casso... sync on pc writing when changed tree | commitdiff
2020-08-13 Luke Kenneth Casso... sync on read of regfile ports tree | commitdiff
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing tree | commitdiff
2020-08-11 Luke Kenneth Casso... sigh, remove yet another int regfile read port tree | commitdiff
2020-08-11 Luke Kenneth Casso... massive reduction in gate count by using alternative... tree | commitdiff
2020-08-11 Luke Kenneth Casso... reduce regfile port usage for INT and FAST tree | commitdiff
2020-08-11 Luke Kenneth Casso... prepare write ports to be shared tree | commitdiff
2020-08-11 Luke Kenneth Casso... move write regfile picker creation to new function tree | commitdiff
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile tree | commitdiff
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports tree | commitdiff
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-09 Luke Kenneth Casso... write pulse in issuer tree | commitdiff
2020-08-09 Luke Kenneth Casso... fix combinatorial loop in ldst compunit tree | commitdiff
2020-08-09 Luke Kenneth Casso... use rising edge detection on st go_i/rel_o tree | commitdiff
2020-08-09 Luke Kenneth Casso... add logical test issuer case tree | commitdiff
2020-08-09 Luke Kenneth Casso... get rid of MSR read combinatorial loop tree | commitdiff
2020-08-09 Luke Kenneth Casso... delay go_st by one cycle, break combinatorial loop tree | commitdiff
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-05 Luke Kenneth Casso... add div test cases into test_issuer.py tree | commitdiff
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and... tree | commitdiff
2020-08-04 Luke Kenneth Casso... read/set pc outside of FSM so that DMI interface can... tree | commitdiff
2020-08-04 Luke Kenneth Casso... whoops must output NIA not PC to debug DMI query in... tree | commitdiff
2020-08-04 Luke Kenneth Casso... allow instruction to run if initiated whilst "stopped... tree | commitdiff
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim tree | commitdiff
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