add srcstep and correct PC-advancing during Sub-PC looping in ISACaller
[soc.git] / src / soc / simulator / test_mul_sim.py
2020-07-21 Luke Kenneth Casso... spurious imports of FHDLTestCase, should be from nmutil
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... whoops forgot that the mul pipeline is actually a pipel...
2020-07-06 Luke Kenneth Casso... continue mul unit test debugging
2020-07-06 Luke Kenneth Casso... add mullw test to qemu sim
2020-07-06 Luke Kenneth Casso... add first simulator mul test