tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
[soc.git] / src / soc / simulator / test_sim.py
2020-08-04 Luke Kenneth Casso... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-08-01 Luke Kenneth Casso... add quick test of litex bios IMM64 macro
2020-07-31 Luke Kenneth Casso... add more instructions to litex trampoline test (not...
2020-07-30 Luke Kenneth Casso... add trampoline test from litex
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... add test_nop general test case
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... spurious imports of FHDLTestCase, should be from nmutil
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-09 Luke Kenneth Casso... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... allow qemu to stop at specified end point
2020-07-08 Luke Kenneth Casso... add a simple addis test (regression)
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add ATTN unit test
2020-07-06 Luke Kenneth Casso... continue mul unit test debugging
2020-07-06 Luke Kenneth Casso... improve debug for test_sim.py
2020-07-06 Luke Kenneth Casso... add first simulator mul test
2020-07-05 Luke Kenneth Casso... fix qemu trap test
2020-06-19 Luke Kenneth Casso... do mix-in for test_sim.py so that jacob can write some...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth Casso... move test_sim.py unit tests to different class (split)
2020-06-17 Luke Kenneth Casso... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth Casso... add loop example, required a bit of munging.
2020-06-14 Luke Kenneth Casso... add sim-qemu test for byte-reversed LD/ST
2020-06-14 Luke Kenneth Casso... add another LD/ST example to qemu-sim test,
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... first cut at qemu memory dump and compare
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-09 Luke Kenneth Casso... experimenting with CR/LR/XER etc in qemu
2020-06-08 Michael NolanAdd register assertions, fix broken tests
2020-06-08 Michael NolanRestore test_sim.py, begin modifying it for testing...
2020-05-07 Luke Kenneth Casso... move unused simulator code out the way
2020-04-20 Tobias Platentestcase fo mulli
2020-04-20 Tobias Platentestcase for addis
2020-04-20 Tobias Platenadd with carry cleanup and test case
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-09 Tobias Platenfix 'Object is not an nMigen signal' error in test_sim.py
2020-04-06 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-06 Jacob LifshayMerge branch 'fix-tests'
2020-04-06 Jacob Lifshayalmost all tests work
2020-03-26 Michael NolanAdd tests for subfic and neg
2020-03-26 Michael NolanSub instruction working
2020-03-25 Michael NolanDirectly compare simulator with qemu
2020-03-25 Michael NolanAssemble whole program instead of instruction by instru...
2020-03-23 Michael NolanImplement load and store of bytes, halfwords, and words
2020-03-23 Michael NolanAdd support for extended/indexed ld/st
2020-03-23 Michael NolanAdd memory loads and stores to simulator
2020-03-23 Michael NolanBegin adding backend simulator