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identifying locations where big/little endian is in place, adding args
[soc.git]
/
src
/
soc
/
simulator
/
test_sim.py
2020-07-09
Luke Kenneth Casso...
identifying locations where big/little endian is in...
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2020-07-08
Luke Kenneth Casso...
resolving bigendian/littleendian modes in qemu sim
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2020-07-08
Luke Kenneth Casso...
allow qemu to stop at specified end point
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2020-07-08
Luke Kenneth Casso...
add a simple addis test (regression)
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
add ATTN unit test
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2020-07-06
Luke Kenneth Casso...
continue mul unit test debugging
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2020-07-06
Luke Kenneth Casso...
improve debug for test_sim.py
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2020-07-06
Luke Kenneth Casso...
add first simulator mul test
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2020-07-05
Luke Kenneth Casso...
fix qemu trap test
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2020-06-19
Luke Kenneth Casso...
do mix-in for test_sim.py so that jacob can write some...
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2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-18
Luke Kenneth Casso...
debugging test_issuer.py general test cases
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2020-06-18
Luke Kenneth Casso...
move test_sim.py unit tests to different class (split)
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2020-06-17
Luke Kenneth Casso...
update test_sim.py to do a simple execution loop: decod...
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2020-06-17
Luke Kenneth Casso...
add loop example, required a bit of munging.
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2020-06-14
Luke Kenneth Casso...
add sim-qemu test for byte-reversed LD/ST
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2020-06-14
Luke Kenneth Casso...
add another LD/ST example to qemu-sim test,
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2020-06-14
Luke Kenneth Casso...
reasonably certain that the careful and slow use of...
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2020-06-12
Luke Kenneth Casso...
first cut at qemu memory dump and compare
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2020-06-10
Luke Kenneth Casso...
whitespace
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2020-06-09
Luke Kenneth Casso...
experimenting with CR/LR/XER etc in qemu
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2020-06-08
Michael Nolan
Add register assertions, fix broken tests
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2020-06-08
Michael Nolan
Restore test_sim.py, begin modifying it for testing...
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2020-05-07
Luke Kenneth Casso...
move unused simulator code out the way
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2020-04-20
Tobias Platen
testcase fo mulli
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2020-04-20
Tobias Platen
testcase for addis
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2020-04-20
Tobias Platen
add with carry cleanup and test case
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2020-04-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-09
Tobias Platen
fix 'Object is not an nMigen signal' error in test_sim.py
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2020-04-06
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-06
Jacob Lifshay
Merge branch 'fix-tests'
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2020-04-06
Jacob Lifshay
almost all tests work
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2020-03-26
Michael Nolan
Add tests for subfic and neg
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2020-03-26
Michael Nolan
Sub instruction working
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2020-03-25
Michael Nolan
Directly compare simulator with qemu
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2020-03-25
Michael Nolan
Assemble whole program instead of instruction by instru...
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2020-03-23
Michael Nolan
Implement load and store of bytes, halfwords, and words
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2020-03-23
Michael Nolan
Add support for extended/indexed ld/st
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2020-03-23
Michael Nolan
Add memory loads and stores to simulator
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2020-03-23
Michael Nolan
Begin adding backend simulator
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