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Fix SVP64 translator to yield the unaltered instruction
[soc.git]
/
src
/
soc
/
sv
/
trans
/
svp64.py
2021-02-13
Cesar Strauss
Fix SVP64 translator to yield the unaltered instruction
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2021-02-01
Luke Kenneth Casso...
construct the assembly-code prefix and base v3.0B in...
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2021-01-31
Luke Kenneth Casso...
start an ISACaller SVP64 unit test
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2021-01-28
Luke Kenneth Casso...
move svp64 reg-decode function to more appropriate...
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2021-01-27
Luke Kenneth Casso...
move SVP64RM CSV class to new module
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2021-01-27
Luke Kenneth Casso...
also read LDST RM files
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2021-01-25
Luke Kenneth Casso...
extra comments in svp64
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2021-01-24
Luke Kenneth Casso...
changing svp64 asm syntax to use / instead of . as...
24jan2021_ls180
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2021-01-23
Luke Kenneth Casso...
move sanity-checks, add mode into svp64_rm
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2021-01-23
Luke Kenneth Casso...
cleanup on aisle 3 - simplify sv_mode svp64
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2021-01-23
Luke Kenneth Casso...
check src/dest mask exist if zeroing, svp64
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2021-01-23
Luke Kenneth Casso...
add predicate-result svp64 decoding
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2021-01-23
Luke Kenneth Casso...
add svp64 saturation decoding
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2021-01-23
Luke Kenneth Casso...
start decoding modes in svp64
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2021-01-23
Luke Kenneth Casso...
and now for something completely different...
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2021-01-23
Luke Kenneth Casso...
add elwidth encoding svp64, add more debug-print
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2021-01-23
Luke Kenneth Casso...
add svp64 subvl encoding
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2021-01-23
Luke Kenneth Casso...
add in svp64 predicate mask encoding
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2021-01-23
Luke Kenneth Casso...
capture CR 3 and 5 bit sv encodings
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2021-01-23
Luke Kenneth Casso...
start decoding EXTRA2/3
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2021-01-23
Luke Kenneth Casso...
start decoding sv EXTRAs and identifying them
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2021-01-23
Luke Kenneth Casso...
start to read RM CSV files
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2021-01-23
Luke Kenneth Casso...
add beginnings of svp64 assembly translator
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