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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
sv
/
trans
/ svp64.py
2021-04-23
Luke Kenneth Casso...
more openpower import conversion
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2021-04-03
Cesar Strauss
Disallow unknown encmodes in SVP64 Assembly
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2021-04-02
Cesar Strauss
Put sanity check inside the existing '2Pred' case,...
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2021-04-02
Cesar Strauss
Enforce explicit src/dest masks on CR twin-predication
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2021-04-02
Cesar Strauss
Disallow mixing of sm=xx and/or dm=xx with m=xx on...
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2021-04-02
Cesar Strauss
Disallow dm=xx on single predication
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2021-04-02
Cesar Strauss
Fix typo
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2021-04-02
Cesar Strauss
Really enforce sm=xx not being allowed on single-pred
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2021-04-02
Cesar Strauss
Keep mask mode flags separate
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2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
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2021-03-30
Luke Kenneth Casso...
skip 1-pred check if m= used in SVP64Asm
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2021-03-22
Luke Kenneth Casso...
read predicate mask from correct point in SVP64Asm
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2021-03-22
Luke Kenneth Casso...
add SVP64Asm option for "m=" to set both src and dest...
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2021-03-21
Luke Kenneth Casso...
naah. back to "sv." syntax for SVP64 assembly
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2021-03-20
Luke Kenneth Casso...
sort out predicate zeroing in ISACaller
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2021-03-20
Luke Kenneth Casso...
attempting to add src/dest-zeroing to ISACaller
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2021-03-14
Luke Kenneth Casso...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14
Luke Kenneth Casso...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-13
Luke Kenneth Casso...
add setvl-to-long converter in SVP64Asm (sigh)
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2021-03-12
Luke Kenneth Casso...
decoding of svp64 reg by name has to occur after immedi...
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2021-03-11
Luke Kenneth Casso...
add understanding of LDST immediates to SVP64ASM
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2021-02-21
Luke Kenneth Casso...
add comments for Mode field in SVP64Asm
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2021-02-21
Cesar Strauss
Use symbolic values as field sizes
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2021-02-21
Cesar Strauss
Replace all hardcoded shifts into RM by usage of SVP64R...
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2021-02-20
Cesar Strauss
Assemble the SV64 prefix from its subfields using SVP64...
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2021-02-20
Luke Kenneth Casso...
fix SVP64Asm Rc=1 assembly
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2021-02-16
Cesar Strauss
Fix MSB0 issues for SVP64
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2021-02-13
Cesar Strauss
Fix SVP64 translator to yield the unaltered instruction
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2021-02-01
Luke Kenneth Casso...
construct the assembly-code prefix and base v3.0B in...
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2021-01-31
Luke Kenneth Casso...
start an ISACaller SVP64 unit test
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2021-01-28
Luke Kenneth Casso...
move svp64 reg-decode function to more appropriate...
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2021-01-27
Luke Kenneth Casso...
move SVP64RM CSV class to new module
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2021-01-27
Luke Kenneth Casso...
also read LDST RM files
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2021-01-25
Luke Kenneth Casso...
extra comments in svp64
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2021-01-24
Luke Kenneth Casso...
changing svp64 asm syntax to use / instead of . as...
24jan2021_ls180
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2021-01-23
Luke Kenneth Casso...
move sanity-checks, add mode into svp64_rm
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2021-01-23
Luke Kenneth Casso...
cleanup on aisle 3 - simplify sv_mode svp64
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2021-01-23
Luke Kenneth Casso...
check src/dest mask exist if zeroing, svp64
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2021-01-23
Luke Kenneth Casso...
add predicate-result svp64 decoding
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2021-01-23
Luke Kenneth Casso...
add svp64 saturation decoding
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2021-01-23
Luke Kenneth Casso...
start decoding modes in svp64
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2021-01-23
Luke Kenneth Casso...
and now for something completely different...
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2021-01-23
Luke Kenneth Casso...
add elwidth encoding svp64, add more debug-print
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2021-01-23
Luke Kenneth Casso...
add svp64 subvl encoding
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2021-01-23
Luke Kenneth Casso...
add in svp64 predicate mask encoding
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2021-01-23
Luke Kenneth Casso...
capture CR 3 and 5 bit sv encodings
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2021-01-23
Luke Kenneth Casso...
start decoding EXTRA2/3
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2021-01-23
Luke Kenneth Casso...
start decoding sv EXTRAs and identifying them
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2021-01-23
Luke Kenneth Casso...
start to read RM CSV files
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2021-01-23
Luke Kenneth Casso...
add beginnings of svp64 assembly translator
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