update pinmux submodule, rename to "fabric"
[soc.git] / src / soc /
2022-07-06 Luke Kenneth Casso... update pinmux submodule, rename to "fabric" master
2022-07-06 Luke Kenneth Casso... add fabric compatibility mode
2022-07-05 Luke Kenneth Casso... MulOutputData was only 64-bit output not 128-bit
2022-07-04 Luke Kenneth Casso... add signal for resetting trap internal state (kaivb...
2022-07-04 Luke Kenneth Casso... set msr_o.data not msr_o Record in trap main_stage.py
2022-06-26 Luke Kenneth Casso... adapt TRAP function in main state pipeline to put KAIVB
2022-06-26 Luke Kenneth Casso... store KAIVB SPR 850 in TRAP Pipeline
2022-06-26 Luke Kenneth Casso... reduce icache/dcache TLB sizes
2022-06-26 Luke Kenneth Casso... update trap test_pipe_caller.py to use up-to-date test...
2022-06-26 Luke Kenneth Casso... missing module argument to TestRunner execute
2022-06-26 Luke Kenneth Casso... convert trap test_pipe_caller.py to consistent format
2022-05-23 Andrey MiroshnikovChange usage of WB sel for individual control
2022-05-01 Luke Kenneth Casso... split out front of div into separate stage, still too...
2022-04-30 Luke Kenneth Casso... add missing module
2022-04-30 Luke Kenneth Casso... split off CR0/XER production in DIV Function Unit into...
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious...
2022-04-30 Cesar StraussImplement transparent read port option on the XOR wrapp...
2022-04-29 Jacob Lifshayfix waay-too-precise error requirements
2022-04-29 Luke Kenneth Casso... add option to set small cache sizes in
2022-04-29 Jacob Lifshayadd comment
2022-04-29 Jacob Lifshayfix so HDL works for 5, 8, 16, 32, and 64-bits.
2022-04-29 Jacob LifshayHDL works for io_width=5
2022-04-28 Cesar StraussTest simultaneous transparent reads and partial writes
2022-04-28 Jacob Lifshayadd docs for clz
2022-04-28 Jacob Lifshayadd WIP HDL version of goldschmidt division -- it's...
2022-04-28 Jacob Lifshaymove GoldschmidtDivState
2022-04-28 Jacob Lifshayadd FIXME comments
2022-04-28 Jacob Lifshayadd the goldschmidt sqrt/rsqrt algorithm, still need...
2022-04-27 Jacob Lifshayimproved goldschmidt division algorithm parameter optim...
2022-04-27 Jacob Lifshaysplit out non-derived params into separate class withou...
2022-04-27 Jacob Lifshaysplit out n_hat as separate property
2022-04-27 Jacob Lifshayadd default_cost_fn
2022-04-27 Jacob Lifshaymove GoldschmidtDivParams.get to bottom of class
2022-04-27 Jacob Lifshayrename _goldschmidt_div_ops to GoldschmidtDivState...
2022-04-26 Jacob Lifshaygoldschmidt division works! still needs better paramete...
2022-04-26 Jacob Lifshayfix goofed __init__.py file name
2022-04-25 Jacob Lifshayworking on goldschmidt_div_sqrt.py
2022-04-23 Jacob Lifshayworking on goldschmidt division algorithm
2022-04-22 Luke Kenneth Casso... whitespace
2022-04-22 Jacob Lifshayadd WIP goldschmidt division algorithm
2022-04-17 Cesar StraussImplement a 1W/1R register file, XOR style
2022-04-17 Cesar StraussFormal proof of pseudo 1W/2R SRAM
2022-04-17 Cesar StraussAdd transparent option for the full read port
2022-04-17 Cesar StraussImplement a pseudo 1W/2R memory
2022-04-16 Luke Kenneth Casso... reduce dcache/icache number of ways, to fit into ECP5...
2022-04-16 Tobias Platenpart two of issuer_fix: read pspec.microwatt_old and...
2022-04-16 Cesar StraussCheck non-transparent 1W/1R SRAM wrapper
2022-04-16 Cesar StraussEnable read port for non-transparent memories
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc
2022-04-16 Tobias Platenpart one of issuer_fix: add parameter to issuer_verilog.py
2022-04-16 Cesar StraussAdd port declarations to the SRAM wrappers
2022-04-16 Cesar StraussChange write lane signal from one-hot to binary
2022-04-16 Luke Kenneth Casso... whoops, WBASyncBridge ack signal not wired up!
2022-04-16 Luke Kenneth Casso... select width is data_width // data granularity.
2022-04-16 Cesar StraussSynchronize LVT state, completing the induction proof
2022-04-16 Cesar StraussSync proof state with downstream memories
2022-04-16 Luke Kenneth Casso... put the old microwatt compatibility back
2022-04-16 Luke Kenneth Casso... blegh.
2022-04-15 Cesar StraussComplete moving the induction support into the DUT
2022-04-15 Cesar StraussFix incorrect signal widths
2022-04-15 Cesar StraussMove part of formal proof to the implementation
2022-04-14 Luke Kenneth Casso... add option Spec to XICS ICP/ICS to be able to activate...
2022-04-14 Luke Kenneth Casso... move IRQLine out because that makes soc dependent on...
2022-04-14 Luke Kenneth Casso... 80 char limit, remove creation of stall from ack/cyc...
2022-04-14 Raptor Engineering... wb_async: Allow different feature fields for master...
2022-04-14 Raptor Engineering... Add separate memory clock register to SYSCON
2022-04-12 Tobias Platenissuer.py: add microwatt_old and microwatt_debug options
2022-04-11 Raptor Engineering... Separate core and nest clocks in Microwatt SYSCON
2022-04-11 Raptor Engineering... Add initial wrapper for Wishbone asynchronous bridge...
2022-04-10 Cesar StraussBegin a formal proof of the LVT-based 1W/1R wrapper
2022-04-10 Cesar StraussImplement 1W/1R with a transparent (or not) read port.
2022-04-10 Cesar StraussImplement a true 1W/1R memory from 1RW blocks
2022-04-09 Luke Kenneth Casso... add a new make target for setting coldboot firmware...
2022-04-08 Luke Kenneth Casso... syntax error
2022-04-08 Luke Kenneth Casso... add dram to SysCon
2022-04-08 Luke Kenneth Casso... add SPI offset to microwatt syscon
2022-04-06 Luke Kenneth Casso... only add clock-settings on ECP5 due to special SPI...
2022-04-04 Luke Kenneth Casso... add tempfile to uart16550 wrapper which defines DATA_BU...
2022-04-04 Luke Kenneth Casso... allow direction-setting on each of dq0-3 in Tercel...
2022-04-03 Luke Kenneth Casso... cant stand the practice of putting docstrings *after...
2022-04-03 Cesar StraussExtend the proof to a non-transparent port
2022-04-03 Cesar StraussRun formal proof on both types (even/odd) of phased...
2022-04-03 Cesar StraussComplete the formal proof of the pseudo dual port SRAM
2022-04-03 Cesar StraussImplement a debug port on the pseudo 1W/1R SRAM
2022-04-03 Cesar StraussFormal proof of the phased write dual port memory wrapper
2022-04-03 Luke Kenneth Casso... correct default to zero string not zero int
2022-04-03 Luke Kenneth Casso... add alternative pc_reset argument to issuer_verilog.py
2022-04-03 Luke Kenneth Casso... fix some of instantiation errors in opencores_ethmac.py
2022-04-02 Raptor Engineering... Fix opencores EthMAC module wiring
2022-04-02 Cesar StraussImplement transparent read ports on the phased write...
2022-04-02 Cesar StraussImplement and test a "phased write port" memory
2022-03-31 Luke Kenneth Casso... invert cs_n pin in Tercel
2022-03-30 Luke Kenneth Casso... nope, default features in Tercel WB Buses need to not...
2022-03-29 Luke Kenneth Casso... add bus.err to list of default Wishbone signals in...
2022-03-29 Luke Kenneth Casso... byte-reverse Tercel read/write data and config bus...
2022-03-29 Luke Kenneth Casso... set clock freq Constant length to 32-bit in Tercel.
2022-03-29 Luke Kenneth Casso... self.specials does not exist, Instances must be added...
2022-03-29 Luke Kenneth Casso... more sorting out wishbone names in Tercel
2022-03-29 Luke Kenneth Casso... fix names of Instance signals in Tercel
2022-03-29 Luke Kenneth Casso... sort out variable names in Tercel