attempting to add SPRs to rfid test
[soc.git] / src /
2020-07-01 Luke Kenneth Casso... attempting to add SPRs to rfid test
2020-07-01 Luke Kenneth Casso... add OP_SC
2020-07-01 Luke Kenneth Casso... trap test check results
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion
2020-07-01 Luke Kenneth Casso... add in trap compunit
2020-07-01 Luke Kenneth Casso... add rfid and td/tw trap test
2020-07-01 Luke Kenneth Casso... continue debugging trap pipeline
2020-07-01 Luke Kenneth Casso... debugging trap pipeline
2020-07-01 Luke Kenneth Casso... start running trap unit test, fixing errors
2020-06-30 Luke Kenneth Casso... add lte ltu for use by twi and other trap functions
2020-06-30 Luke Kenneth Casso... add in pseudocode keyword into mdwn isa files
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... add README for fu directory
2020-06-29 Luke Kenneth Casso... use correct ALUHelpers in div test
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-29 Luke Kenneth Casso... first unit test for div
2020-06-29 Luke Kenneth Casso... add ignore for parsetab.py
2020-06-29 Luke Kenneth Casso... add autogenerated do not commit comment
2020-06-29 Luke Kenneth Casso... separate out divide by zero cases
2020-06-29 Luke Kenneth Casso... update OV and OV32 ISACaller flags if overflow occurs
2020-06-29 Luke Kenneth Casso... attempting to add overflow setting in ISACaller
2020-06-29 Luke Kenneth Casso... whoops, hex parser digits are in multiples of 4 bits
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Luke Kenneth Casso... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth Casso... need args to WishboneArbiter, match data width size
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth Casso... add test instruction memory
2020-06-28 Luke Kenneth Casso... add readonly option to TestMemory
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-28 Luke Kenneth Casso... parameterise minerva i-cache
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs
2020-06-28 Luke Kenneth Casso... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth Casso... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... name issue in Pi2LSUI
2020-06-26 Luke Kenneth Casso... whitespace and imports
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth Casso... correct address in pi2ls
2020-06-26 Luke Kenneth Casso... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth Casso... add in LenExpand shift/mask
2020-06-26 Luke Kenneth Casso... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth Casso... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth Casso... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth Casso... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth Casso... unit test broken is ok :)
2020-06-26 Luke Kenneth Casso... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth Casso... dynamically specify wishbone layout (no longer hardcode...
2020-06-26 Luke Kenneth Casso... add reconfigureable Load/Store class
2020-06-26 Luke Kenneth Casso... extra parameterification of minerva LoadStoreUnits
2020-06-25 Luke Kenneth Casso... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth Casso... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth Casso... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth Casso... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
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