2020-10-01 |
Cole Poirier | icache.py add missing comb signal assignments per https... |
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2020-10-01 |
Luke Kenneth Casso... | arg CacheRam read output needs delay by 1 cycle |
tree | commitdiff |
2020-10-01 |
Luke Kenneth Casso... | do not pass cache row array around, just the current row |
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2020-10-01 |
Luke Kenneth Casso... | revert bug in icache wishbone ack |
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2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
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2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
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2020-10-01 |
Cesar Strauss | Add GTKWave document to test_compunit_fsm |
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2020-09-30 |
Luke Kenneth Casso... | add I2C into ls180 |
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2020-09-30 |
Luke Kenneth Casso... | add ASIC version of I2C Master |
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2020-09-30 |
Luke Kenneth Casso... | clean up row store and wb adr in icache |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | hmm only set wishbone address if ack is actually received |
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2020-09-30 |
Luke Kenneth Casso... | add more debug prints in icache |
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2020-09-30 |
Luke Kenneth Casso... | remove more reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | remove reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | comb on wr_index not sync |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | start removing reviewed comments |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | use same constant name (confusing otherwise) |
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2020-09-30 |
Luke Kenneth Casso... | need asserts |
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2020-09-30 |
Luke Kenneth Casso... | halve the number of icache lines for now |
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2020-09-30 |
Luke Kenneth Casso... | use Repl rather than for-loop to copy bit |
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2020-09-30 |
Luke Kenneth Casso... | move loop invariant test out of loop |
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2020-09-30 |
Luke Kenneth Casso... | reduce size of ilang file by a factor of FIVE |
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2020-09-30 |
Luke Kenneth Casso... | store tag in temp signal |
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2020-09-30 |
Luke Kenneth Casso... | reduce gate usage by getting cache row only not entire... |
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2020-09-30 |
Luke Kenneth Casso... | fix read_tag to use word_select correctly |
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2020-09-30 |
Luke Kenneth Casso... | forgot to add PLRUs as submodules |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix combinatorial loop with by testing temp... |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix is_last_row_addr, get_next_row_addr |
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2020-09-29 |
Cole Poirier | icache.py trying to sort out test failure, added r... |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
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2020-09-29 |
Cole Poirier | icache.py fix rarange |
tree | commitdiff |
2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
tree | commitdiff |
2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
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2020-09-28 |
Luke Kenneth Casso... | reduce not-connected IO pins |
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2020-09-28 |
Luke Kenneth Casso... | missing pspec |
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2020-09-28 |
Luke Kenneth Casso... | connect SDRAM dqm to wrdata_mask |
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2020-09-28 |
Luke Kenneth Casso... | lots of sorting out iopads |
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2020-09-28 |
Luke Kenneth Casso... | add "nocore" option to build verilog |
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2020-09-28 |
Luke Kenneth Casso... | switch off internal gpio (testing) |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | rewrite ilang file after litex ls180 build |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | had to over-ride the wishbone functions on C4M TAP |
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2020-09-27 |
Cole Poirier | icache.py fix translation mistake |
tree | commitdiff |
2020-09-27 |
Cesar Strauss | Convert yet another few tests to be able to use latest... |
tree | commitdiff |
2020-09-27 |
Luke Kenneth Casso... | add Makefile for creating ls180.il |
tree | commitdiff |
2020-09-27 |
Luke Kenneth Casso... | rename sys_clk_i to clk_24_i |
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2020-09-27 |
Luke Kenneth Casso... | add clock selection mechanism |
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2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | do not use simdec2 in test_pipe_caller |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | fix annoying alu test_pipe_caller bug, missing asmcode |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add alternative PowerDecode2 to branch test_pipe_caller |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | try svf test of DMI MSR |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | make check of LDSTMode.update conditional in PowerDecoder2 |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add ls180io.py |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add openocd script to fire off svf test |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | get openocd svf test running, replicating jtag test |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | put test into "server" mode for connecting with openocd |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | class-ify jtagremote |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | send/receive jtagremote protocol |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | basic client/server socket example |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add openocd configs |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | reduce sdram pins to smaller address and only 1 cs_n |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | only enable pads connections for ls180 for now |
tree | commitdiff |
2020-09-25 |
Cole Poirier | icache.py fix several subtle bugs that were lines that... |
tree | commitdiff |
2020-09-25 |
Cole Poirier | wb_types.py add reset value of 0b11111111 for WBSelType... |
tree | commitdiff |
2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | do not have to use uart_litex gpio_litex names |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | add comments |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | enable GPIO pads through C4M JTAG |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | c4m iopad integration working |
tree | commitdiff |
2020-09-24 |
Cole Poirier | icache.py add some missing lines from icache.vhdl,... |
tree | commitdiff |
2020-09-24 |
Cole Poirier | mem_types.py wb_types.py add name constructor to all... |
tree | commitdiff |
2020-09-24 |
Cole Poirier | icache.py fixed all errors that raised python exception... |
tree | commitdiff |
2020-09-24 |
Cesar Strauss | Fix whitespace, remove unused imports |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | brackets round imports looks cleaner? |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | add jtag c4m pins which gives us a way to connect IO... |
tree | commitdiff |
2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | cs_n and cke in sdram need to match in length |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | change litex sdram pinouts to ASIC type |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | redo litex SDCard to send out data/cmd o/i/en pins |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | sort out GPIO with i/o/oe in ls180 |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add ls180 pinmap text file |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | attempt GPIO bi-directional |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add I2C master to ls180 |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add 2 PWMs (quick, easy to do) |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
tree | commitdiff |
2020-09-22 |
Jacob Lifshay | Revert "disable pia in div tests" |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add openocd.cfg experiment |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | create a JTAG platform and connect it up. jtagremote... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtagremote to litex sim, add new "variant" to core... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | link litex ls180soc JTAG pads |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtag wishbone and jtag ports to libresoc litex... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtag interface to issuer_verilog |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add sys_rst to Clock Reset Generator |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add JTAG IOpads and rename rst to sys_rst |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add similar platforms to ls180.py |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add JTAG bus module |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | split out dmi2jtag into own unit test |
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