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too much debug info going past, so add the test registers to the
[soc.git] / src /
2020-07-24 Luke Kenneth Casso... too much debug info going past, so add the test registe... tree | commitdiff
2020-07-24 Luke Kenneth Casso... missed import tree | commitdiff
2020-07-24 Luke Kenneth Casso... calling the test dictionary from the constructor is... tree | commitdiff
2020-07-24 Luke Kenneth Casso... whoops spelling tree | commitdiff
2020-07-24 Luke Kenneth Casso... add the div pipe kind plus prog.assembly to the assert... tree | commitdiff
2020-07-24 Luke Kenneth Casso... call test_write_ilang only once - ends up being called... tree | commitdiff
2020-07-24 Luke Kenneth Casso... fix how long div tests run, de-comment FSM and DivPipeCore tree | commitdiff
2020-07-24 Luke Kenneth Casso... argh! work-in-progress breaking / fixing how to do... tree | commitdiff
2020-07-24 Luke Kenneth Casso... whoops must add DivTestCasesLong to get it to produce... tree | commitdiff
2020-07-24 Luke Kenneth Casso... remove bad hack calling trunc_divs/trunc_mods tree | commitdiff
2020-07-24 Luke Kenneth Casso... re-enable commented-out div unit tests tree | commitdiff
2020-07-24 Luke Kenneth Casso... split out "all" div into separate unit test (takes... tree | commitdiff
2020-07-24 Luke Kenneth Casso... reduce variable size, continuation not needed tree | commitdiff
2020-07-24 Luke Kenneth Casso... comment about timeline does not exist tree | commitdiff
2020-07-24 Luke Kenneth Casso... ah ha! not using "with" was not calling the "close... tree | commitdiff
2020-07-24 Luke Kenneth Casso... read into a BytesIO to avoid "too many open files" tree | commitdiff
2020-07-24 Luke Kenneth Casso... whitespace / comments tree | commitdiff
2020-07-24 Luke Kenneth Casso... restore modification to caller.py from reversion of... tree | commitdiff
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller" tree | commitdiff
2020-07-24 Luke Kenneth Casso... bug found in pseudocode reader when assembly code has... tree | commitdiff
2020-07-24 Luke Kenneth Casso... code review comments for trap and proof tree | commitdiff
2020-07-24 Luke Kenneth Casso... made it clear what is meant by the slice numbering... tree | commitdiff
2020-07-24 Samuel A. Falvo IIRefactorin of common code tree | commitdiff
2020-07-24 Samuel A. Falvo IIAddress code review comments tree | commitdiff
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller tree | commitdiff
2020-07-23 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting tree | commitdiff
2020-07-23 Luke Kenneth Casso... try SDRAM SDR tree | commitdiff
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide tree | commitdiff
2020-07-23 Luke Kenneth Casso... begin core in running state tree | commitdiff
2020-07-23 Luke Kenneth Casso... try different MEMTEST_xxx sizes with 64 bit bus width tree | commitdiff
2020-07-23 Jacob Lifshayadd all div* and mod* instructions to test_pipe_caller tree | commitdiff
2020-07-22 Jacob Lifshayworking on fsm tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Jacob Lifshayformat code tree | commitdiff
2020-07-22 Luke Kenneth Casso... re-add CRG (clock reset generator) tree | commitdiff
2020-07-22 Luke Kenneth Casso... missing ports from issuer, when doing verilog tree | commitdiff
2020-07-22 Luke Kenneth Casso... add clock domain using snippet taken from random file tree | commitdiff
2020-07-22 Luke Kenneth Casso... cleanup in litex core.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... update comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add dummy irq set/get tree | commitdiff
2020-07-22 Luke Kenneth Casso... add boot-helper.S etc from microwatt litex core tree | commitdiff
2020-07-22 Luke Kenneth Casso... set additional MSR bits according to v3.0B spec when... tree | commitdiff
2020-07-22 Luke Kenneth Casso... use (new) MSRb and PIb which has auto-bigendian numbers tree | commitdiff
2020-07-22 Luke Kenneth Casso... sigh, auto-create some little/big-endian classes for... tree | commitdiff
2020-07-22 Luke Kenneth Casso... missed import of Builder, set cpu_type to "None" tempor... tree | commitdiff
2020-07-22 Luke Kenneth Casso... begin converting litex sim to libre-soc tree | commitdiff
2020-07-22 Luke Kenneth Casso... whoops forgot field accessor tree | commitdiff
2020-07-22 Luke Kenneth Casso... do not use wildcard import tree | commitdiff
2020-07-22 Luke Kenneth Casso... start from vexriscv sim.py from tree | commitdiff
2020-07-22 Luke Kenneth Casso... correct syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... first version of litex core (to be submitted upstream... tree | commitdiff
2020-07-22 Luke Kenneth Casso... whoops typo, 63-start not 3-start (doh) tree | commitdiff
2020-07-22 Luke Kenneth Casso... field number ordering wrong way round? tree | commitdiff
2020-07-22 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... review trap main_stage.py modifications: we are not... tree | commitdiff
2020-07-22 Luke Kenneth Casso... comments, add page spec numbers for branch ops into... tree | commitdiff
2020-07-22 Luke Kenneth Casso... add comment headings with spec page numbers tree | commitdiff
2020-07-22 Luke Kenneth Casso... comment on op.insn ordering tree | commitdiff
2020-07-22 Luke Kenneth Casso... code-shuffle, add comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input... tree | commitdiff
2020-07-22 Luke Kenneth Casso... inline comments in trap proof tree | commitdiff
2020-07-22 Luke Kenneth Casso... note that traptype MUST increase in bitwidth correspond... tree | commitdiff
2020-07-22 Luke Kenneth Casso... fix branch main_stage proof, add ctr 32-bit, fix BCREG tree | commitdiff
2020-07-22 Luke Kenneth Casso... rework branch proof to use br_input_record tree | commitdiff
2020-07-22 Luke Kenneth Casso... update README for pipe_data.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports tree | commitdiff
2020-07-22 Luke Kenneth Casso... comments on what goes into CommonPipeSpec tree | commitdiff
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions. tree | commitdiff
2020-07-22 Samuel A. Falvo IIPEP8 compliance tree | commitdiff
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage tree | commitdiff
2020-07-22 Jacob Lifshayfix test_div_state_fsm tree | commitdiff
2020-07-21 Samuel A. Falvo IICompleted SC FV properties tree | commitdiff
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec tree | commitdiff
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from tree | commitdiff
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties. tree | commitdiff
2020-07-21 Luke Kenneth Casso... convert branch pipeline to use msr/cia as immediates tree | commitdiff
2020-07-21 Luke Kenneth Casso... put set_msr and set_cia back in for now tree | commitdiff
2020-07-21 Luke Kenneth Casso... interesting bug in test_compunit.py when there are... tree | commitdiff
2020-07-21 Luke Kenneth Casso... testing if MultiCompUnit can handle no input regs ... tree | commitdiff
2020-07-21 Luke Kenneth Casso... disable cxxsim for now tree | commitdiff
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record tree | commitdiff
2020-07-21 Luke Kenneth Casso... set ISACaller.msr rather than namespace[MSR] tree | commitdiff
2020-07-21 Luke Kenneth Casso... when running an exception (trap) after "reset" must... tree | commitdiff
2020-07-21 Luke Kenneth Casso... spurious imports of FHDLTestCase, should be from nmutil tree | commitdiff
2020-07-21 Luke Kenneth Casso... whitespace tree | commitdiff
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into... tree | commitdiff
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware tree | commitdiff
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning tree | commitdiff
2020-07-21 Luke Kenneth Casso... corrections to trap proof see tree | commitdiff
2020-07-21 Luke Kenneth Casso... use alias for msr_i in trap proof tree | commitdiff
2020-07-21 Luke Kenneth Casso... correct trap spec page interrupt ref tree | commitdiff
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style tree | commitdiff
2020-07-20 Samuel A. Falvo IIFormal properties for RFID. tree | commitdiff
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op. tree | commitdiff
2020-07-20 Cesar StraussRemove extra yield from test case. tree | commitdiff
2020-07-19 Luke Kenneth Casso... do not start core in terminated mode tree | commitdiff
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py tree | commitdiff
2020-07-19 Luke Kenneth Casso... expose core_stop_i to outside as well tree | commitdiff
2020-07-19 Luke Kenneth Casso... set go_insn_i to non-resetless tree | commitdiff
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