Add code, commented-out, for TRAP so as to not break test_caller.py
[soc.git] / src /
2020-06-20 colepoirierAdd code, commented-out, for TRAP so as to not break...
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-19 Luke Kenneth Casso... move trunc_div and trunc_rem to nmutil
2020-06-19 Luke Kenneth Casso... add comments on trunc_div and trunc_rem
2020-06-19 Luke Kenneth Casso... add divide-by-zero test to test_div_sim.py
2020-06-19 Luke Kenneth Casso... add docstring comment for SelectableInt
2020-06-19 Luke Kenneth Casso... add test_0_moduw and correct name to trunc_rem
2020-06-19 Luke Kenneth Casso... add abs SelectableInt unit test (very quick)
2020-06-19 Luke Kenneth Casso... add SelectableInt.abs
2020-06-19 Luke Kenneth Casso... add another bad hack in parser.py which identifies...
2020-06-19 Luke Kenneth Casso... add in really bad hack which calls trunc_div or trunc_mod
2020-06-19 Luke Kenneth Casso... add trunc_div and trunch_rem to decoder helpers
2020-06-19 Luke Kenneth Casso... auto-assign needs to use concat / selectconcat
2020-06-19 Luke Kenneth Casso... whoops detected page name wrong, for special case fixed...
2020-06-19 Luke Kenneth Casso... bit of a mess. getting carry recognised and output...
2020-06-19 Luke Kenneth Casso... add auto-assign mode detecting uninitialised variable...
2020-06-19 Luke Kenneth Casso... div needs to be floordiv
2020-06-19 Luke Kenneth Casso... add true and floor div to SelectableInt
2020-06-19 Luke Kenneth Casso... add simulator test for divw
2020-06-19 Luke Kenneth Casso... do mix-in for test_sim.py so that jacob can write some...
2020-06-19 Luke Kenneth Casso... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-19 Luke Kenneth Casso... parameterise LoadStoreUnitInterface to be expandable
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer
2020-06-18 Luke Kenneth Casso... got loop example operational by noting when PC fastreg...
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth Casso... get instructions immediately from assembly code
2020-06-18 Luke Kenneth Casso... move test_sim.py unit tests to different class (split)
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC
2020-06-18 Luke Kenneth Casso... whoops generate core ilang not TestIssuer
2020-06-18 Luke Kenneth Casso... use while / exception in test_compunit loop
2020-06-18 Luke Kenneth Casso... investigating mtocrf/mtcrf issue
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-17 Luke Kenneth Casso... add bug reference to mtocrf/mtcrf name decoding
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth Casso... add comment/assembly decode in power enums
2020-06-17 Luke Kenneth Casso... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth Casso... add loop example, required a bit of munging.
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... got fed up of adding arguments to ISACaller / ISA,...
2020-06-17 Luke Kenneth Casso... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth Casso... comment ISACaller setup
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-17 Luke Kenneth Casso... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth Casso... add optional instruction memory
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth Casso... move debug statements to check function
2020-06-16 Luke Kenneth Casso... hack LD/ST ad/st together, allow PC to be set externally
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add ports to TestMemory
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth Casso... weird: adding TestMemory with no port causes nmigen...
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM
2020-06-16 Luke Kenneth Casso... update popcount docstring
2020-06-15 Luke Kenneth Casso... start trying to fill in some comments in Minerva L1...
2020-06-15 Luke Kenneth Casso... whitespace cleanup
2020-06-15 Luke Kenneth Casso... imports and syntax errors fixed (found test_cache.py)
2020-06-15 Luke Kenneth Casso... more whitespace
2020-06-15 Luke Kenneth Casso... more whitespace on minerva (no unit tests, so cannot...
2020-06-15 Luke Kenneth Casso... whitespace cleanup, remove minerva DataSelector class
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests...
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth Casso... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth Casso... unit tests showing byte-reverse works
2020-06-14 Luke Kenneth Casso... add sim-qemu test for byte-reversed LD/ST
2020-06-14 Luke Kenneth Casso... add in byte-reverse from op PowerDecode2 field
2020-06-14 Luke Kenneth Casso... error in address width (truncated) in setting up L0Cach...
2020-06-14 Luke Kenneth Casso... error in naming that ended up in gtkwave from a proxy
2020-06-14 Luke Kenneth Casso... add another LD/ST example to qemu-sim test,
2020-06-14 Luke Kenneth Casso... add byte-reversal on LD and ST in L0CacheBuffer
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
2020-06-12 Luke Kenneth Casso... first cut at qemu memory dump and compare
2020-06-12 Luke Kenneth Casso... note possible BE/LE mode needed for memory reads/writes
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
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