2020-06-20 |
colepoirier | Add code, commented-out, for TRAP so as to not break... |
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2020-06-19 |
Luke Kenneth Casso... | whitespace update |
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2020-06-19 |
Luke Kenneth Casso... | move trunc_div and trunc_rem to nmutil |
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2020-06-19 |
Luke Kenneth Casso... | add comments on trunc_div and trunc_rem |
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2020-06-19 |
Luke Kenneth Casso... | add divide-by-zero test to test_div_sim.py |
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2020-06-19 |
Luke Kenneth Casso... | add docstring comment for SelectableInt |
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2020-06-19 |
Luke Kenneth Casso... | add test_0_moduw and correct name to trunc_rem |
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2020-06-19 |
Luke Kenneth Casso... | add abs SelectableInt unit test (very quick) |
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2020-06-19 |
Luke Kenneth Casso... | add SelectableInt.abs |
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2020-06-19 |
Luke Kenneth Casso... | add another bad hack in parser.py which identifies... |
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2020-06-19 |
Luke Kenneth Casso... | add in really bad hack which calls trunc_div or trunc_mod |
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2020-06-19 |
Luke Kenneth Casso... | add trunc_div and trunch_rem to decoder helpers |
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2020-06-19 |
Luke Kenneth Casso... | auto-assign needs to use concat / selectconcat |
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2020-06-19 |
Luke Kenneth Casso... | whoops detected page name wrong, for special case fixed... |
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2020-06-19 |
Luke Kenneth Casso... | bit of a mess. getting carry recognised and output... |
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2020-06-19 |
Luke Kenneth Casso... | add auto-assign mode detecting uninitialised variable... |
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2020-06-19 |
Luke Kenneth Casso... | div needs to be floordiv |
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2020-06-19 |
Luke Kenneth Casso... | add true and floor div to SelectableInt |
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2020-06-19 |
Luke Kenneth Casso... | add simulator test for divw |
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2020-06-19 |
Luke Kenneth Casso... | do mix-in for test_sim.py so that jacob can write some... |
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2020-06-19 |
Luke Kenneth Casso... | add TODO comments to upgrade L0CacheBuffer to a new... |
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2020-06-19 |
Luke Kenneth Casso... | parameterise LoadStoreUnitInterface to be expandable |
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2020-06-18 |
Jacob Lifshay | div pipe completed except for tests |
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2020-06-18 |
Jacob Lifshay | finish code to calculate the 64-bit output of the div... |
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2020-06-18 |
Jacob Lifshay | actually remove todo comment for manually checking... |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Jacob Lifshay | fix bug and manually check div overflow code against... |
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2020-06-18 |
Luke Kenneth Casso... | enable general test cases in test_issuer |
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2020-06-18 |
Luke Kenneth Casso... | got loop example operational by noting when PC fastreg... |
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2020-06-18 |
Luke Kenneth Casso... | use different way to pass instructions to test_issuer... |
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2020-06-18 |
Luke Kenneth Casso... | debugging test_issuer.py general test cases |
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2020-06-18 |
Luke Kenneth Casso... | get instructions immediately from assembly code |
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2020-06-18 |
Luke Kenneth Casso... | move test_sim.py unit tests to different class (split) |
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2020-06-18 |
Luke Kenneth Casso... | slightly hacky way to keep an eye on the PC |
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2020-06-18 |
Luke Kenneth Casso... | whoops generate core ilang not TestIssuer |
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2020-06-18 |
Luke Kenneth Casso... | use while / exception in test_compunit loop |
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2020-06-18 |
Luke Kenneth Casso... | investigating mtocrf/mtcrf issue |
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2020-06-18 |
Jacob Lifshay | working on adding rest of stage classes for div pipeline |
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2020-06-17 |
Luke Kenneth Casso... | add bug reference to mtocrf/mtcrf name decoding |
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2020-06-17 |
Luke Kenneth Casso... | decoding assembly instruction name, move to separate... |
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2020-06-17 |
Luke Kenneth Casso... | getting sim instruction decoder to reproduce asm instru... |
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2020-06-17 |
Luke Kenneth Casso... | add comment/assembly decode in power enums |
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2020-06-17 |
Luke Kenneth Casso... | update test_sim.py to do a simple execution loop: decod... |
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2020-06-17 |
Luke Kenneth Casso... | add loop example, required a bit of munging. |
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2020-06-17 |
Luke Kenneth Casso... | get fu compunit test to use ISACaller instruction-memory |
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2020-06-17 |
Luke Kenneth Casso... | got fed up of adding arguments to ISACaller / ISA,... |
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2020-06-17 |
Luke Kenneth Casso... | split execute and setup of ISACaller instruction execution |
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2020-06-17 |
Luke Kenneth Casso... | comment ISACaller setup |
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2020-06-17 |
Luke Kenneth Casso... | start to add in independent execution into ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add a fake program counter to ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | use an independent power decoder in ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add "respect_pc" boolean to ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add optional instruction memory |
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2020-06-17 |
Luke Kenneth Casso... | split out TestIssuer into separate module |
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2020-06-17 |
Luke Kenneth Casso... | remove unneeded yield |
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2020-06-17 |
Luke Kenneth Casso... | enable all tests again in test_core.py and test_issuer.py |
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2020-06-17 |
Luke Kenneth Casso... | got test_issuer FSM operating. bit of a hack |
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2020-06-17 |
Luke Kenneth Casso... | debugging test_issuer, getting FSM working |
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2020-06-17 |
Luke Kenneth Casso... | output to issuer_simulator.vcd |
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2020-06-16 |
Luke Kenneth Casso... | add first version unit test for TestIssuer |
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2020-06-16 |
Luke Kenneth Casso... | reduce instruction depth to 6 bits in TestIssuer |
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2020-06-16 |
Luke Kenneth Casso... | move debug statements to check function |
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2020-06-16 |
Luke Kenneth Casso... | hack LD/ST ad/st together, allow PC to be set externally |
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2020-06-16 |
Luke Kenneth Casso... | move check regs in simple core to separate function |
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2020-06-16 |
Luke Kenneth Casso... | move test core reg set up into separate function |
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2020-06-16 |
Luke Kenneth Casso... | set up a TestIssuer class with a FSM for doing instruct... |
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2020-06-16 |
Luke Kenneth Casso... | add ports to TestMemory |
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2020-06-16 |
Luke Kenneth Casso... | add beginnings of TestIssuer class, to issue instructio... |
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2020-06-16 |
Luke Kenneth Casso... | weird: adding TestMemory with no port causes nmigen... |
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2020-06-16 |
Luke Kenneth Casso... | refer to signals directly in Test Core |
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2020-06-16 |
Luke Kenneth Casso... | add test instruction memory SRAM |
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2020-06-16 |
Luke Kenneth Casso... | update popcount docstring |
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2020-06-15 |
Luke Kenneth Casso... | start trying to fill in some comments in Minerva L1... |
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2020-06-15 |
Luke Kenneth Casso... | whitespace cleanup |
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2020-06-15 |
Luke Kenneth Casso... | imports and syntax errors fixed (found test_cache.py) |
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2020-06-15 |
Luke Kenneth Casso... | more whitespace |
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2020-06-15 |
Luke Kenneth Casso... | more whitespace on minerva (no unit tests, so cannot... |
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2020-06-15 |
Luke Kenneth Casso... | whitespace cleanup, remove minerva DataSelector class |
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2020-06-15 |
Luke Kenneth Casso... | have to set up addr/st rel-go link before setting up... |
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2020-06-15 |
Luke Kenneth Casso... | add in memory setup/check but disable LDST Unit Tests... |
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2020-06-15 |
Luke Kenneth Casso... | move setup/check memory into helper functions for use... |
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2020-06-15 |
Luke Kenneth Casso... | whoops LDSTCompUnit was identified as a Function.ALU... |
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2020-06-15 |
Luke Kenneth Casso... | add in TstL0CacheBuffer but disable temporarily |
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2020-06-14 |
Luke Kenneth Casso... | add optional LDSTFunctionUnit to compunits |
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2020-06-14 |
Luke Kenneth Casso... | unit tests showing byte-reverse works |
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2020-06-14 |
Luke Kenneth Casso... | add sim-qemu test for byte-reversed LD/ST |
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2020-06-14 |
Luke Kenneth Casso... | add in byte-reverse from op PowerDecode2 field |
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2020-06-14 |
Luke Kenneth Casso... | error in address width (truncated) in setting up L0Cach... |
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2020-06-14 |
Luke Kenneth Casso... | error in naming that ended up in gtkwave from a proxy |
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2020-06-14 |
Luke Kenneth Casso... | add another LD/ST example to qemu-sim test, |
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2020-06-14 |
Luke Kenneth Casso... | add byte-reversal on LD and ST in L0CacheBuffer |
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2020-06-14 |
Luke Kenneth Casso... | reasonably certain that the careful and slow use of... |
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2020-06-13 |
Cesar Strauss | Wait for all active rel signals to be high, and only... |
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2020-06-12 |
Luke Kenneth Casso... | first cut at qemu memory dump and compare |
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2020-06-12 |
Luke Kenneth Casso... | note possible BE/LE mode needed for memory reads/writes |
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2020-06-12 |
Luke Kenneth Casso... | update ld/st test to see what is going on |
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2020-06-12 |
Luke Kenneth Casso... | tracking down what looks like an error in the Simulator... |
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2020-06-12 |
Luke Kenneth Casso... | debug printout of sim and hardware memory, shows mismat... |
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2020-06-12 |
Luke Kenneth Casso... | use ALUHelpers in LDSTCompUnit test |
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2020-06-11 |
Luke Kenneth Casso... | some ugly hacks that get LD/ST immediate working |
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