tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
[soc.git] / src /
2020-08-04 Luke Kenneth Casso... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-04 Luke Kenneth Casso... whitespace after autopep8 messed up
2020-08-04 Luke Kenneth Casso... msr and pc moved to "state" in PowerDecode2
2020-08-04 Luke Kenneth Casso... whoops must output NIA not PC to debug DMI query in...
2020-08-04 Luke Kenneth Casso... allow instruction to run if initiated whilst "stopped...
2020-08-04 Luke Kenneth Casso... cycle through INT regs, read and debug in litex sim
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim
2020-08-04 Luke Kenneth Casso... single-step and print out PC using DMI in litex sim
2020-08-04 Luke Kenneth Casso... get litex sim to kick off a "STEP" via the DMI interfac...
2020-08-04 Luke Kenneth Casso... connect up a DMI FSM to litex sim
2020-08-04 Luke Kenneth Casso... more remove wildcard imports
2020-08-04 Luke Kenneth Casso... do not use wildcard imports
2020-08-04 Luke Kenneth Casso... adding litex sim experimentation.
2020-08-04 Samuel A. Falvo IIRemove XXX; this seems done otherwise.
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Luke Kenneth Casso... add extra port for debug read of int regs via DMI
2020-08-03 Luke Kenneth Casso... pass state (MSR/PC) around between PowerDecode2, DMI...
2020-08-03 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=446
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-08-03 Tobias PlatenLDSTSplitter: report exception
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Tobias PlatenTstDataMerger2
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-08-03 Luke Kenneth Casso... move debug to record
2020-08-03 Samuel A. Falvo IIWIP: check MB > ME and select mask appropriately
2020-08-02 Luke Kenneth Casso... convert microwatt core_debug.vhdl to nmigen
2020-08-02 Luke Kenneth Casso... add debug dir
2020-08-01 Luke Kenneth Casso... add quick test of litex bios IMM64 macro
2020-08-01 Luke Kenneth Casso... add rlwnm test showing that shift rot OP_RLC proof...
2020-08-01 Luke Kenneth Casso... line-length / whitespace
2020-08-01 Luke Kenneth Casso... expand out for-loop setting up input record subset
2020-07-31 Luke Kenneth Casso... reorg DecodeB in power_decoder2.py to sign-extend immed...
2020-07-31 Luke Kenneth Casso... add more instructions to litex trampoline test (not...
2020-07-31 Luke Kenneth Casso... restrict external port list further in test_issuer
2020-07-31 Luke Kenneth Casso... missed go_i/rel_o rename
2020-07-31 Samuel A. Falvo IIWIP: more debugging signals for inspection
2020-07-30 Samuel A. Falvo IIWIP: rlwinm/rlwnm/rlwimi-type proofs
2020-07-30 Tobias Platenbegin work on TestCase for two DataMergers/Cache
2020-07-30 Tobias Platenadd CacheRecord
2020-07-30 Luke Kenneth Casso... core_start/stop/endian were inverted (output)
2020-07-30 Luke Kenneth Casso... ha! have to explicitly specify the ports when writing...
2020-07-30 Luke Kenneth Casso... add trampoline test from litex
2020-07-30 Luke Kenneth Casso... set sel line in minerva instruction fetch
2020-07-30 Luke Kenneth Casso... ha! found source of XICS test bug: wishbone stb was...
2020-07-29 Luke Kenneth Casso... more exploratory testing of XICS, joining ICP and ICS...
2020-07-29 Tobias Platenmodified LDSTSplitter to conform to PortInterface
2020-07-29 Luke Kenneth Casso... forgot to rename ad/st in LDSTCompUnitRecord
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-29 Luke Kenneth Casso... start on test joining XICS ICS to ICP
2020-07-29 Luke Kenneth Casso... tidyup XICS, identify (potential?) bug?
2020-07-29 Luke Kenneth Casso... move CR test out of subtest indentation
2020-07-29 Luke Kenneth Casso... move SHIFTROT test out of subtest indentation
2020-07-29 Luke Kenneth Casso... move actual ALU test out of subTest indentation just...
2020-07-29 Luke Kenneth Casso... whitespace
2020-07-29 Jacob Lifshayclean up branch test_pipe_caller
2020-07-29 Jacob Lifshayclean up alu test_pipe_caller
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayclean up some tests
2020-07-29 Jacob Lifshayformat some tests
2020-07-29 Jacob Lifshayadd code for skipping test cases
2020-07-28 Jacob Lifshayclean up div pipe tests to allow them to be run in...
2020-07-28 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-28 Jacob Lifshayfix test_pipe_ilang.py
2020-07-28 Luke Kenneth Casso... use ctx.op compare (and muxid) in shiftrot proof
2020-07-28 Jacob Lifshaysplit out ilang tests
2020-07-28 Jacob Lifshayformat code
2020-07-28 Luke Kenneth Casso... add preliminary investigative test of XICS ICS
2020-07-28 Luke Kenneth Casso... tidyup/comments in trap proof
2020-07-27 Luke Kenneth Casso... add 2nd part of XICS interrupt interface
2020-07-27 Luke Kenneth Casso... fix trap proof, and trap main_stage, and pseudocode...
2020-07-27 Luke Kenneth Casso... shorten expected_ to exp_, gets line-length down
2020-07-26 Samuel A. Falvo IIMTMSR(D) properties.
2020-07-26 Luke Kenneth Casso... start on conversion of xics.vhdl to nmigen
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... add test_nop general test case
2020-07-26 Luke Kenneth Casso... activate some of new accumulator-based tests in test_issuer
2020-07-26 Luke Kenneth Casso... do not need lod_l.q | lsto_l.q can just use lsd_l.q
2020-07-26 Luke Kenneth Casso... argh add yet another latch to detect when LD/ST has...
2020-07-26 Luke Kenneth Casso... sigh, issue with detection/waiting for LD/ST CompUnit
2020-07-26 Luke Kenneth Casso... convert LDST test to accumulator style
2020-07-26 Luke Kenneth Casso... convert Branch test to accumulator style
2020-07-26 Luke Kenneth Casso... convert SPR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert TRAP test to accumulator style
2020-07-26 Luke Kenneth Casso... remove FHDLTestCase
2020-07-26 Luke Kenneth Casso... convert CR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert mul test to accumulator style
2020-07-26 Luke Kenneth Casso... convert shift_rot test to new base accumulator style
2020-07-26 Luke Kenneth Casso... convert logical test case to new base class accumulator...
2020-07-26 Luke Kenneth Casso... move run_test_program to base class and rename to ...
2020-07-26 Luke Kenneth Casso... convert ALU to new accumulator style
2020-07-26 Luke Kenneth Casso... again, move large heavily-indented code-block in div...
2020-07-26 Luke Kenneth Casso... run subtest, indentation getting too large, move to...
2020-07-26 Luke Kenneth Casso... get div compunit test running (use new way to accumulat...
2020-07-26 Luke Kenneth Casso... use new test accumulator class in div tests
2020-07-26 Luke Kenneth Casso... add common test base class for "accumulating" tests...
2020-07-25 Luke Kenneth Casso... remove old div overflow test, keep microwatt version
2020-07-25 Luke Kenneth Casso... hilarious. only just caught a bug where overflow was...
2020-07-25 Luke Kenneth Casso... comb += missing
2020-07-25 Luke Kenneth Casso... add CR0 regression, expected 0b10 actual 0b11
2020-07-25 Luke Kenneth Casso... add regression test 8, DivPipeCore producing spurious...
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